The wrong choice is at GMAC1 RGMII delayline control.
Fixes: 2627dcd2c9e9("net: ethernet: stmmac: dwmac-rk: Add gmac support for rk3588")
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ibc31f4f8b0f8c23c7ca3b290f3d95ba34f03c05f
This is required by android hwc for dev/dri/card128.
Change-Id: Ia0159b877f7d8b2bb5cecf3b352b67d9c76c7c97
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
1. support buffer_size set by user
2. support assigned chn
3. support udma read
4. support buffer address set by userspace
Need to update test_pcie and test-pcie-ep-new.
New test command:
1. run ./test-pcie-ep-new 500 1024 chn_num buffer_address both on RC and EP first
Release buffer use dma channel number = chn_num.
if buffer_address = 0
pcie_dma_buffer_address get from DT reserved memory
else
pcie_dma_buffer_address = buffer_address
2. run ./test-pcie 1 1000 1024 1 chn_num on RC
The last "1" means enable PCIe udma read, "0" means write.
RC read from EP use dma channel number = chn_num.
3. run ./test-pcie 2 1000 1024 1 chn_num on EP
EP read from RC with offset = buffer count * buffer size.
4. check version by:
cat /sys/kernel/debug/pcie/pcie_trx | grep version
5. 1024 means set buffer size to 1MB.
Change-Id: I7613037924659c75014d19b6c4845e096a56d295
Signed-off-by: Simon Xue <xxm@rock-chips.com>
These controllers use the same clk for tx/rx.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ie9a0adb950cdc584761c1079cb45e58d5eafccfb
Reserved 8M for cma heap, the node' name will be used as heap' name.
Also add ramoops and logo node.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I50654b1122126bb54092e3933d1a36cadf8d4ec5
When enter low temperature mode, system monitor update opp table, then
check and change the current voltage for cpu, but now the opp voltage
inside cpu_opp_helper() may be old, the current voltage may be changed
back to old value. Move the volt_adjust_mutex out of dev_pm_opp_set_rate()
so that the opp voltage inside cpu_opp_helper() will be latest.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I9a91775dc9b5443e4b47b4255de6e21133c32404
If read multiple channels at the same time, channel 1 will
error, add assert when start saradc as a workaround.
Change-Id: Iababf604b200555a46a96e1ca0bc7108c6df8680
Signed-off-by: Simon Xue <xxm@rock-chips.com>
The RK3588 SoC has seven channels TS-ADC(TOP, BIG_CORE0, BIG_CORE1,
LITTEL_CORE, CENTER, GPU, and NPU).
Change-Id: I940a10c8062ba73876f2dfd133ab8ea60ad3a799
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Just print out POST_BUF_EMPTY_INT err irq if it happened.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: Ia1d3747c94d432ca8451f38e10d32a82bbf7b958
It's optional on RK3588 platform which support dsm only.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I3cbe3a3bb7789eab2a279403d359a58f1fd85c7b
On RK3568: this bit is Auto gating enable
on RK3588: this bit is gating disable(we must set it to 1 when afbc
enable)
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: If689c587c6df9e1e8c6ff670d30e62c53b621194
Configuration is flexible than hard code, and minimal changes.
Change-Id: I15835fcbf198252410feb3feb6080ca047388ce1
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Remove a regulator-fixed node without gpio enable pin from evb dtsi,
move them to next level board dt file.
The vcc3v3_lcd0_n regulator is a software virtual regulator for camera
module to push high/low level from a gpio but through regulator
enable/disable.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I1f587fe1ca0ef9d31c6cba5362c1912b7208f293
