On some chip, HDMI post PLL is not stable when it's vco is 1080M,
but it work ok when vco is 270M. We use a efuse bit to distinguish
these chip.
Change-Id: I143363d67e60747ee52d405edace3ec611de3e6e
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Inno hdmi phy post pll is enabled by default on rk3228, it's need to
manual power down post pll if uboot logo is not shown.
Change-Id: I7ed4de2eae2d723f390dae44281281b9e81f4e1d
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
There are many factors affecting the clock phase, including clock
rate, temperature, logic voltage and silicon process, etc. But clock
rate is the most significant one here, and the driver should be aware
of the change of the clock rate. As mmc controller need a fixed phase
after tuning was completed, at least before explicitly doing re-tune,
so this patch try to restore the clock phase by monitoring the event
of rate change.
Change-Id: Id1ccdfd2e8d4e2eb9f6a1923b3813138dbaf99f7
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
(cherry picked from https://patchwork.kernel.org/patch/10269525/)
aptina/imx/ov_camera_module.c:
Fix this warning: this if clause does not guard... [-Wmisleading-indentation]
Change-Id: I788d4d4d04dd2b0b7c41e1a041e9084c62b1975c
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
in addition,
resolve all the conflicts;
rename all the configs and macros that have a same name in midgard/;
fix a compiling error.
Change-Id: I5abc8c925049e087c59b66da57c82aac3092be71
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
we can power off the bandgap to reduce power consumption.
Change-Id: I7959e6f1d38a6abca70d6d904264668a19ace920
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This change adds usb-phy support for rk3308 SoC and amend related
phy Documentation.
Change-Id: I953af94fb4d55d79ae1cba624a04fb4b84e019f6
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The commit dc71e51944 ("usb: dwc2: make otg manage lowlevel
hw on its own") aimed to control the clk and phy power for
otg mode, but it also introduced lost of new problems, so we
revert it.
This patch only controls phy power for otg mode, it can fix
the dwc2 udc start fail issue with the following error log:
dwc2_hsotg_init_fifo: timeout flushing fifos (GRSTCTL=80000430)
dwc2_core_reset() HANG! Soft Reset GRSTCTL=80000001
bound driver configfs-gadget
dwc2_core_reset() HANG! Soft Reset GRSTCTL=80000001
Change-Id: Id6996aecab7f0aaaf12530b7a377144e23ef1667
Signed-off-by: William Wu <william.wu@rock-chips.com>
This reverts commit dc71e51944.
We found that this commit will cause at least three issue:
1. On RK3126C Tablet, plug in OTG cable and U disk first,
then power on the Tablet, the system will hang because
of dwc2 interrupt storm.
2. On RK3328-EVB, connect usb to PC first, then power on
the board, the system will hang because of dwc2 interrup
store.
3. On Linux system, the OTG Host mode can't detect U disk.
The root cause is that this patch will diable the controller
clk at the end of probe if OTG work as OTG mode, and only
enable the clk again in dwc2_hsotg_udc_start(). However,
the dwc2 interrupt is enabled in dwc2_hcd_init() during probe,
so the dwc2 interrupt maybe triggered but the interrupt pending
state can't be cleared because that the clk has been disabled.
This cause dwc2 interrupt storm problem.
On the other hand, for Linux system, it may config OTG work
as OTG mode, but it never calls dwc2_hsotg_udc_start() to
enable the controller clk becasue there is no gadget application.
So the clk never be enabled, and casue OTG Host mode fail
to detect the U disk.
Change-Id: Id3463225e0232de7078de1e9d39470a6d5e2cea4
Signed-off-by: William Wu <william.wu@rock-chips.com>
add devfreq and devfreq_cooling feature for gpio-fan and then
it can be used as thermal cooling device to support IPA thermal
policy.
Change-Id: I376faa485625ac41276df9bbac8188ea8d664b36
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
add support for rgb panel or rgb covert to other interface panel.
Change-Id: I190ce6e08d38f794ecabb863e0def5e74890f75a
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
There are two clocks between armclk and pll_apll on px30,
but there may be only one clock on some Socs, so it will
get a error pll clock.
Change-Id: I34116a1ec824b884d3745082f3546cd9ab4c0d21
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Add constants and callback functions for the dwmac on rk3308 soc.
The base structure is the same, but registers and the bits in
them moved slightly, and add the clk_mac_speed for the select
of mac speed.
Change-Id: Ieaea3ade9e51d5118f0eb855d8e02febfb2275d1
Signed-off-by: David Wu <david.wu@rock-chips.com>
The MMC sample and drv clock for rockchip platforms are derived from
the bus clock output to the MMC/SDIO card. So it should never happens
that the clk rate is zero given it should inherits the clock rate from
its parent. If something goes wrong and makes the clock rate to be zero,
the calculation would be wrong but may still make the mmc tuning process
work luckily. However it makes people harder to debug when the following
data transfer is unstable.
Change-Id: Ifeb4c063cb73e0a444fd8819ef3128256331cd7a
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from https://patchwork.kernel.org/patch/10258071/)
Opp rate is used to calc power in thermal framework, so we record
this rate instead of real clock rate.
Devfreq is not ready in target() when use performance governor, so
we need record opp rate in probe().
Change-Id: Iec1918ad5d12124b9f112964f247339e0d50645f
Signed-off-by: Liang Chen <cl@rock-chips.com>
In the bandwidth tension environment when close win2, vop will access
the freed memory lead to iommu pagefault. so we add this reset to workaround.
Change-Id: I22b0c0f145d042e3aaf98fb45ffff6304c93963c
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Because when enable uboot logo display, vop_crtc_enable() will not be
called when power on, this will lead to some vop initial like
axi channel and some debug irq will not be enabled. so we move some
config to vop_initial() and call from vop_crtc_loader_protect().
Change-Id: I86f02e2e7d12b78cce17e278baaf6dff93137167
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
some version vop unsupport pixel alpha add scale, this case
will lead to display error and post empty.
Change-Id: I32820a14292b46ce61fd30bfccdaa5e4f635de49
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
The most pins of rk3308 are 2bits iomux, but the banks's register
width is 0x8.
Change-Id: I3305810b3f75febd6ec7a933b65e3c9d50f003dd
Signed-off-by: David Wu <david.wu@rock-chips.com>
This adds the necessary data for handling io voltage domains on the rk3308.
As interesting tidbit, the rk3308 contains one iodomain area at grf,
Change-Id: Ife72a284a8926d02ef5df7a422d41924494d0300
Signed-off-by: David Wu <david.wu@rock-chips.com>
Otherwise, clk_gpu won't be disabled actually in the runtime.
Change-Id: I92787a5e23bfb92f5a79efda92c130832751cc3b
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
The commit 9d9491a7da ("mmc: dw_mmc: Fix the DTO timeout calculation")
and commit 4c2357f57d ("mmc: dw_mmc: Fix the CTO timeout calculation")
made changes, which cause multiply overflow for 32-bit systems. The
broken
timeout calculations leads to unexpected ETIMEDOUT errors and causes
stacktrace splat (such as below) during normal data exchange with
SD-card.
| Running : 4M-check-reassembly-tcp-cmykw2-rotatew2.out -v0 -w1
| - Info: Finished target initialization.
| mmcblk0: error -110 transferring data, sector 320544, nr 2048, cmd
| response 0x900, card status 0x0
DIV_ROUND_UP_ULL helps to escape usage of __udivdi3() from libgcc and so
code gets compiled on all 32-bit platforms as opposed to usage of
DIV_ROUND_UP when we may only compile stuff on a very few arches.
Lets cast this multiply to u64 type to prevent the overflow.
Change-Id: I45462bac22f946c5129eab0e0d5b22b3ed7ca19d
Fixes: 9d9491a7da ("mmc: dw_mmc: Fix the DTO timeout calculation")
Fixes: 4c2357f57d ("mmc: dw_mmc: Fix the CTO timeout calculation")
Tested-by: Vineet Gupta <Vineet.Gupta1@synopsys.com>
Reported-by: Vineet Gupta <Vineet.Gupta1@synopsys.com> # ARC STAR
9001306872 HSDK, sdio: board crashes when copying big files
Signed-off-by: Evgeniy Didin <Evgeniy.Didin@synopsys.com>
Cc: <stable@vger.kernel.org> # 4.14
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
(cherry picked from c715160225)
Add the clock tree definition for the new RK3308 SoC.
Change-Id: I1c0794b290207d28102e8d30cca13bbbf54ccfb8
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
After a cpufreq transition, update the clockevent's frequency
by fetching the new clock rate from the clock framework and
reprogram the next clock event.
The clock supplying the arm-global-timer on the rk3188 is coming
from the the cpu clock itself and thus changes its rate everytime
cpufreq adjusts the cpu frequency.
Found by code review, real impact not known. Assume what actual
HZ value will be different from expected on platforms using
arm-global-timer as clockevent.
The patch is port of commit 4fd7f9b128 ("ARM: 7212/1: smp_twd:
reconfigure clockevents after cpufreq change") and
commit 2b25d9f64b ("ARM: 7535/1: Reprogram smp_twd based on
new common clk framework notifiers").
Change-Id: I82552f621e30254b9c48f22fb3ebd2866d4476c8
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
