There are many factors affecting the clock phase, including clock
rate, temperature, logic voltage and silicon process, etc. But clock
rate is the most significant one here, and the driver should be aware
of the change of the clock rate. As mmc controller need a fixed phase
after tuning was completed, at least before explicitly doing re-tune,
so this patch try to restore the clock phase by monitoring the event
of rate change.
Change-Id: Id1ccdfd2e8d4e2eb9f6a1923b3813138dbaf99f7
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
(cherry picked from https://patchwork.kernel.org/patch/10269525/)
There are two clocks between armclk and pll_apll on px30,
but there may be only one clock on some Socs, so it will
get a error pll clock.
Change-Id: I34116a1ec824b884d3745082f3546cd9ab4c0d21
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
The MMC sample and drv clock for rockchip platforms are derived from
the bus clock output to the MMC/SDIO card. So it should never happens
that the clk rate is zero given it should inherits the clock rate from
its parent. If something goes wrong and makes the clock rate to be zero,
the calculation would be wrong but may still make the mmc tuning process
work luckily. However it makes people harder to debug when the following
data transfer is unstable.
Change-Id: Ifeb4c063cb73e0a444fd8819ef3128256331cd7a
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from https://patchwork.kernel.org/patch/10258071/)
Add the clock tree definition for the new RK3308 SoC.
Change-Id: I1c0794b290207d28102e8d30cca13bbbf54ccfb8
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
We will need a pll to support all kinds of clock rate requirement
for display. In order not to affect other clocks, remove the cpll
from the parent list of other clocks and only DCLK_VOP can select
cpll as parent.
Change-Id: I69e5e3ca1af66eba5b4cc92b792077ec64f67054
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Phase calculation should be based on the clock rate of these clk,
which inherits the clock rate from their parents. If the parent
goes wrong, it would be orphan node leading all the clk rate to
be zero. This breaks the normal tuning process whilist probing
the card. Fix them!
Change-Id: I7b64748e90684f8ca9710b63f10205d50d24f6d0
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
If change parent to alternate parent and the old parent clock speed is less
than the clock speed of the alternate parent, add dividers first and then
select alternate parent.
If change parent to primary parent, select primary parent first and then
remove dividers.
Change-Id: Ib82de9a936effe5c885639799f3bb5629dc89f8d
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
The gpll clock has not yet been created when its children do enable and
prepare in cru critical talbe, so move its children into pmucru critical
talbe that the gpll clock has been created before its children do enable
and prepare.
Change-Id: If5243326bf1d3c926bb1bb12e56e4b9fc9282762
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
It needs to contains rate and mux clk for gpu composite clk, so that
the clk_composite_set_rate_and_parent function can be called.
Change-Id: I9818df2adbbcf40f616d2ca230cd83ea1ef2c14f
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
The RK817 & RK809 chip is a power management IC for multimedia and handheld
devices. It contains the following components:
- Regulators
- RTC
- Clkout
- Pinctrl
- Powerkey
The RK817 & RK809 core driver is registered as a platform driver and provides
communication through I2C with the host device for the different
components.
The following is the different between the RK817 and the RK809.
1、The dcdc-buck5 is a boost dcdc for RK817 and is a buck for RK809.
2、The RK817 have one switch but The Rk809 have two.
3、The RK817 have a charger and powerpatch function but RK809 not.
Change-Id: I132029c5b28978db7ae06e13c327a1edf70f5b69
Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
