As the emmc is supplyed power by vcc_io, that's 3.3v voltage.
the default 1.8v volatge will cause the emmc error. as the following:
[ 17.096082 ] mmcblk1: error -115 sending stop command, original cmd
response 0x900, card status 0xb00
[ 17.127022 ] mmcblk1: error -110 transferring data, sector 664720, nr
72, cmd response 0x900, card status 0xb00
Remove the mmc-ddr-1_8v to keep the default the 3.3v voltage.
Change-Id: I9e2539d63fd93e72d9febbb311fbd686c5a11d09
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This patch supported the gpu opp table for rk3036.
The gpu clock's parent is DPLL, the default frequency is 400MHz, we need
assign 400MHz for gpu to be better working.
There is a quickly way for testing the gpu scaling frequency.
As following:
"
unset FREQS
read -a FREQS < /sys/class/devfreq/10091000.gpu/available_frequencies
RANDOM=$$$(date +%s)
while true; do
echo userspace > /sys/class/devfreq/10091000.gpu/governor
FREQ=${FREQS[$RANDOM % ${#FREQS[@]} ]}
echo GPU:Now ${FREQ}
echo ${FREQ} > /sys/class/devfreq/10091000.gpu/userspace/set_freq
sleep 1
done
"
Change-Id: Ia8eb3074e457014c497338a0a129551c51450104
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This patch supported the cpu voltage by changed with different
frequency, otherwise we will hit the following error on bootup.
..
[ 5.031516] cpu cpu0: Failed to get cpu_reg
[ 5.047725] cpu cpu0: clk or regulater is unavailable
..
Also, remove the 408M and 600M for rk3036 board, as the pclk_hdmi's parent
on apll, the low frequency will make the pclk be bad for hdmi display.
Change-Id: Ia4aac76a08cad3a59c33cd81065f943201a23a35
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This patch fixes the BT power reported the failure message.
As following:
root@linaro-alip:~# echo 1 > /sys/class/rfkill/rfkill0/state
[ 892.558269] rockchip-pinctrl pinctrl: pin gpio0-19 already requested
by 20060000.serial; cannot claim for wireless-bluetooth
[ 892.571052] rockchip-pinctrl pinctrl: pin-19 (wireless-bluetooth) status -22
...
And for now, the BT can work with this patch.
root@linaro-alip:~# echo 1 > /sys/class/rfkill/rfkill0/state
[ 69.328768] [BT_RFKILL]: ENABLE UART_RTS
[ 69.438540] [BT_RFKILL]: DISABLE UART_RTS
[ 69.443117] [BT_RFKILL]: bt turn on power
...
root@linaro-alip:~# hcitool dev
Devices:
hci0 94:A1:A2:E9:2D:18
And
root@linaro-alip:~# bluetoothctl
[NEW] Controller 94:A1:A2:E9:2D:18 linaro-alip [default]
[bluetooth]# scan on
Discovery started
[CHG] Controller 94:A1:A2:E9:2D:18 Discovering: yes
..
Change-Id: I2148f4203300ab4265fd3ba718f0d3ec0c57e7ca
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
It allows me to set the mac address in the bootloader.
Change-Id: Iad988205c6953e843e62aec67daad52128086324
Signed-off-by: Randy Li <randy.li@rock-chips.com>
There is a combo of a HEVC decoder and a VPU1 decoder at rk3036.
Change-Id: Ia7174cc9e2f2d640a74271077bd62cc68f3482b4
Signed-off-by: Randy Li <randy.li@rock-chips.com>
The serial Flash controller on the rk3036 would request
two clock nodes.
Change-Id: Iaa50c4a25602a68241b0b9b2f186e4c7e55bc3da
Signed-off-by: Randy Li <randy.li@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The clock hevc core will be used to drive the hevc decoder.
Change-Id: Ic1298ce1edd07f86e5c243e3a2c9876481f4cba9
Signed-off-by: Randy Li <randy.li@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
In order to save power and improve the performance, we can add the opp
table for rk3036 SoCs.
Also, make sure the codec works happily, we should ensure the arm/logic
voltage is greater than 1v.
Change-Id: I9aa17be547eb21e5a83c09780356436c3075bae6
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
In order to support the ap6212 module with rockchip wlan driver,
the kylin dts has to change the below for working.
1) We should add the 'supports-sdio' property for mmc tuning,
that's the rockchip private property, not on the upstream.
2) We should add the wifi power control pin and wifi/bt data for dts,
Maybe the history issue, they like the old driver for power
contronlling, the upstream didn't need these for working. we should
remove it in the future.
Change-Id: Id49de7ad77b8658a551a07659a8a2ddc9691874c
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
As the inno-hdmi driver introduced this clock, add it for dts supporting.
Change-Id: I43328a25f0ac72d5a5b7631cc8ff6ce98b78669a
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
In rk3036, the voltages of CPU and GPU are controlled by the same
regulator 'vdd_cpu'.
Here, we fix it to 1.25v to ensure that GPU could work well in
development period.
The actual voltage GPU needs might be much lower, and relative to
the frequency GPU runs at. this would be optimized when we implement
GPU DVFS with devfreq.
Change-Id: Ia25f0a67577fbfe248a25e4d913dc5f14fa40f0d
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
I don't need send for upstream since the rockchip inside kernel
need it for tuning. At least the upstream can work it with dwmmc.
Change-Id: Ia9f0836624e8ef1df225dbc6ad1792ec4fb2abbd
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
1. Remove the useless code about the coordinate after rotation in
the src1 channel.
2. Remove 4 alignment of the src1 channel.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: Ib780c0143a76e4bfc50c0be95e483c503525ab9f
Let configuration start and count be performed at the
same time as much as possible, which can reduce the
interval between the start signal and the data signal,
and can also reduce a start irq.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I529300a083dcd264cc5f25a2069b88601cade83e
If want to use i2c2, we must write i2c2 register bit with 1 at PMUGRF.
Change-Id: Id2b5c1b06c206e43de19fe42024846918fa0b145
Signed-off-by: David Wu <david.wu@rock-chips.com>
When the property "rockchip,grf" of i2c DTS node exists and
the GRF offset is also valid, special bit needs to be configured.
Change-Id: If7ea4185b940ad026ed822b44cfb0c8acda83500
Signed-off-by: David Wu <david.wu@rock-chips.com>
If want to use i2c2, we must write i2c2 register bit with 1 at GRF.
Change-Id: Ia7e59c105647304162bde283a3fb98d9e0db75c3
Signed-off-by: David Wu <david.wu@rock-chips.com>
In some case，log like this:
[ 12.393926] rk3x-i2c ff150000.i2c: irq in STATE_IDLE, ipd = 0x51
[ 12.416592] rk3x-i2c ff150000.i2c: irq in STATE_IDLE, ipd = 0x51
The i2c clock is disabled, so the pending irq clean is not
worked. Disable the interrupt after the i2c jobs were done,
the error log would not happen.
Change-Id: If04a2e2214d675410c67db0f131ee7ef635ddcb4
Signed-off-by: David Wu <david.wu@rock-chips.com>
