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Author SHA1 Message Date
Huang jianzhi
7a9cfb256f Input: add gslx680 touch panel for firefly-rk3288 board 
Change-Id: If273535f595217853009c3b0071010836f7c254e
Signed-off-by: Huang jianzhi <jesse.huang@rock-chips.com>
 2019-03-21 19:13:06 +08:00
Wu Liangqing
856e16bb9a driver: input: touchscreen: add gslx680 for rk3126c d708 
Change-Id: I59594bf83d2de744eb187fe0570366ddb56d8386
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>
 2019-03-21 19:09:08 +08:00
Huang jianzhi
be28ad740b input: touchscreen: vtl_ts: tp firmware dts move to tp_fw.h 
Change-Id: I6279d91f17ecca0c9dcc2355c22737746faee7d4
Signed-off-by: Huang jianzhi <jesse.huang@rock-chips.com>
 2019-03-21 19:00:16 +08:00
Wenping Zhang
da25612009 input: touchscreen: add cy8c40xx touchpad support. 
Change-Id: I765177ee00472e19b8bc6fcbdb79db4ea914f3a9
Signed-off-by: Wenping Zhang <wenping.zhang@rock-chips.com>
 2019-03-21 18:49:47 +08:00
Guochun Huang
57f3ce1f24 input: touchscreen: add touch screen of gslx680 for rk3399-firefly-edp 
Change-Id: Ic4fa205f8f71353c4703d745e96ec9056181c198
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
 2019-03-21 18:49:36 +08:00
Xinhuang Li
3a0f74bcda input: touchscreen: add touch screen of gsl3673 for rk3399-evb 
Change-Id: I16a4e44c75a16aefa153b002bce83392522c7d30
Signed-off-by: Xinhuang Li <buluess.li@rock-chips.com>
 2019-03-21 18:47:06 +08:00
jerry.zhang
9b03d621d5 Input: add gslx680 touch panel for 3399 VR 
Change-Id: I89c3dd181324f6b39e50c40fd404743eab43fe52
Signed-off-by: jerry.zhang <jerry.zhang@rock-chips.com>
 2019-03-21 18:46:49 +08:00
Xu Jianqun
349ecabe2c ARM64: dts: rockchip: support gt9xx for Rockchip platform 
Add support gt9xx driver for Rockchip platform goodix
touchscreen.

There is a goodix driver on upstream but it not work well, so
use the old driver until someone debug the upstream driver.

Change-Id: Id8711a63150da4bdcd8e78f3b2a82157e1b3de4f
Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>
 2019-03-21 17:08:14 +08:00
Aiyoujun
7553c7a85b regulator: xz3216: add driver with xz3216 series of DCDC devices to compile. 
Change-Id: I5883e142c17a60cbba7e37bd4a9303efb3c867bf
Signed-off-by: Aiyoujun <ayj@rock-chips.com>
 2019-03-21 14:28:14 +08:00
Dingqiang Lin
54564cd2a8 soc: rockchip: add flash vendor storage support 
Change-Id: I0261e652161e6a20a4d988c4ddfd7f186ad2200e
Signed-off-by: Dingqiang Lin <jon.lin@rock-chips.com>
 2019-03-20 19:53:12 +08:00
Tao Huang
a27157e5ad soc: rockchip: add android version support 
Add config ANDROID_VERSION, default is Android 8.1.
And add ANDROID_VERSION macro.

Change-Id: I6309ea9118c1d847224f329f6c2d6ab7e073ee5a
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
 2019-03-20 19:51:11 +08:00
Finley Xiao
9836602cd3 soc: rockchip: introduce system status notifier 
This makes dmc driver possible to register a system status notifier and
other drivers possible to call the notifier call-back easily, so that
the dmc driver can change frequency according to different system status.

Change-Id: I1a4fb4649366d75310d2e29f87775bb2d9ca3d67
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2019-03-20 19:49:08 +08:00
Shengfei xu
1caa11c198 suspend: rockchip: set the suspend config to ATF 
Change-Id: I400aa252c24b814e3da7fa6703a4e03a1c90d572
Signed-off-by: Shengfei xu <xsf@rock-chips.com>
 2019-03-20 19:45:41 +08:00
Finley Xiao
feb482f894 soc: rockchip: pvtm: add driver handling Rockchip pvtm 
This patch supports acquiring pvtm values.

Change-Id: I20c0c5a5136371880da1c246b0d71c7a2bddc1d6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2019-03-20 19:45:20 +08:00
Jianqun Xu
7ff1aec28f arm64: dts: rockchip: modify vopb_out_dsi to vopb_out_mipi for rk3399-linux 
Change-Id: I6909bb1bff93a8a37a29ef17b0aac0d430e50b50
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
 2019-03-19 14:37:10 +08:00
Jianqun Xu
e132075aeb arm64: dts: rockchip: include rockchip-system-status.h for rk3399 
Change-Id: I807b38fd38db89f41584dd2cee58bddbc6a34067
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
 2019-03-19 14:35:50 +08:00
Jianqun Xu
80225d46e7 arm64: dts: rockchip: modify pcie_clkreqn to pcie_clkreqn_cpm for rk3399-excavator-sapphire 
Change-Id: I44e6da4fdcae3bd8af0594070922b96ab0f0f2d8
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
 2019-03-19 14:35:32 +08:00
Jianqun Xu
8d1dbdd0ec arm64: dts: rockchip: add supports-emmc for sdhci of rk3399-sapphire 
Change-Id: I7f640335dbc9a1c9831d6bc337422d005ad653df
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
 2019-03-19 14:34:40 +08:00
Jianqun Xu
95fafaf5a8 arm64: dts: rockchip: quote gpu_power_model for rk3399 
Change-Id: Ic188340a29c26bcad94e23d448b4a378892745ea
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
 2019-03-19 10:02:01 +08:00
Jianqun Xu
dc4705a059 arm64: dts: rockchip: quote display_subsystem for rk3399 
Change-Id: I0a68650d9674d2805f661668468718a8777ea325
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
 2019-03-19 10:02:01 +08:00
Wyon Bi
7b2fe6cb75 clk: rockchip: clk-ddr: support DPI connector 
Change-Id: If78851e4908b5f4547cb93496d928d916e893eac
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-18 10:11:56 +08:00
Tony Xie
e85c2739ab PM / devfreq: rockchip_dmc: support wait_complete. 
Change-Id: Ie3f173f632068f261b84a204bbd36b26b10e1981
Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-18 10:11:31 +08:00
YouMin Chen
79820bb8cb clk: rockchip: px30: Add SCLK_DDRCLK for dmc 
Change-Id: I03d6c18829f8895c28bbaef883e187304c48f9aa
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-18 10:11:11 +08:00
Liang Chen
a561d683ac clk: rockchip: rk3228: add clk_ddrc for devfreq of ddr 
Change-Id: I3771e2ef68ab3fa8ad1b7d61a84c7181c693c60f
Signed-off-by: Liang Chen <cl@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-18 10:10:48 +08:00
Jianqun Xu
47742edbbd clk: rockchip: clk-ddr: fix section mismatch problem 
In rockchip_clk_register_ddrclk,

    ifdef CONFIG_ARM
	if (!psci_smp_available())
		return NULL;
    endif

Add "__init" for rockchip_clk_register_ddrclk() to match with
psci_smp_available().

Change-Id: Ib6849e359921c3a937bf8dc4f6547aed353f1071
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-18 10:10:23 +08:00
Jacob Chen
01fe02229e clk: rockchip: do not register ddrclk if PSCI is not enabled on arm32 
ARM32 system can run without trustos,
we should prevent arm_smccc_smc being called in such system.

Change-Id: Ic87b78107b464e3ab8dc72a3ca1fa9a64e358580
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-18 10:10:07 +08:00
YouMin Chen
dbe7301984 clk: rockchip: remove spin_lock in the rockchip_ddrclk_sip_set_rate 
Change-Id: Ia3d04aef8fbf8093c2a3a89a845f948f69c8611f
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-18 10:09:52 +08:00
Tang Yun ping
0be4235294 PM / devfreq: get lcdc type from vop drivers for rk3368 
Change-Id: I9205286f7b4c0d7ecba3bb08a45af3f49225abe5
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-18 10:09:35 +08:00
Tang Yun ping
982114c422 clk: rockchip: using unify parameters for ddr frequency scanning. 
Change-Id: Ibd3befd3cd674af263402f6984ee6d605eb087c8
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-18 10:08:56 +08:00
Tang Yun ping
5145b181c8 clk: rockchip: support setting ddr clock via SIP Version 2 APIs 
1. Add support setting ddr clock via SIP Version 2 APIs
2. RK3288 using SIP Vision 2.

Change-Id: I935e43b1885a96650dc86e3eb6d79de6795062a9
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-18 10:06:01 +08:00
Mark Yao
0d8127f179 drm: add drm_device_get_by_name support 
Change-Id: Ifbd0f403ca2302e9329a16d7b69db5ee056cadf7
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-18 09:29:08 +08:00
Mark Yao
00d3f46c43 rockchip: clk: rk3399: default enable dual pll for vop 
Change-Id: I88a2a549eaafa91e4159f262a5f5838c834a89e9
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-13 17:04:11 +08:00
Elaine Zhang
252980d7d6 clk: rockchip: Modify uart frac divider rule 
Because uart does not have high requirements
for the clk Jitter, the fractional frequency
divider does not need to meet the 20-fold relationship.
(If uart clk rate < 24M,Use 24M as the fractional
clock source.)

Change-Id: I3f55f8a4ba5dc4c950c2742dc914c41e7b6e4ee6
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-13 17:04:11 +08:00
Elaine Zhang
5ee709c798 clk: fractional-divider: Improve fractional divider jitter 
Numerator is greater than 4,the clk jitter is better.

Change-Id: I9fda9ddeb7b26c6b8559b4126e2ad1d29bb850d1
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-13 17:04:10 +08:00
Elaine Zhang
a5ee9af24e clk: rockchip: rk322x: fix up the description error 
Change-Id: I439314c590a7144fab6e33d1fb4f325530669842
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-13 17:04:10 +08:00
Elaine Zhang
2b2be6c065 clk: rockchip: rk3399: export SCLK_I2SOUT_SRC clk ID for i2s 
Change-Id: Ifbcea830e5f49946c1feea3f51d125e6ed566d5f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-13 17:04:10 +08:00
Sugar Zhang
157da43492 clk: rockchip: px30: Export clk id for sclk_i2s0_tx/rx mux 
Change-Id: I697d20fb0c69f9dcd76aaf2d18d666db2241360d
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-13 17:04:09 +08:00
Elaine Zhang
21c2c1cb99 clk: rockchip: add support for pvtm clk 
add pvtm 32K internal clock setting and select enable.

Change-Id: I60225d29e16c5b96f285623260bea475c78a026a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-13 17:04:09 +08:00
Elaine Zhang
8b335da717 clk: rockchip: rk3128: add hclk_sfc 
Change-Id: I20d0975156dc73bcdd02c09b7ecb815d5aca6bc6
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-13 17:04:09 +08:00
Finley Xiao
50dc2b3ad7 clk: rockchip: px30: Add support to set parent rate for vopl dclk 
Change-Id: I208471f938b1795273c4f33ac35b82d667a2b312
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-13 17:04:08 +08:00
Finley Xiao
1a8710858d clk: rockchip: px30: Let npll only provide clock for vopl and gpu 
As npll rate may be changed according to vopl dclk rate on px30.

Change-Id: I4abc042b49ee06436ba5d69dc8adfa9460da37f7
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-13 17:04:08 +08:00
Finley Xiao
8bbf873b1d clk: rockchip: px30: Remove npll from gpu parent clock on px30 
NPLL should provide clock for vopl dclk on px30, and its rate will be
changed according to vopl dclk rate, so GPU can't use npll as parent
on px30.

Change-Id: Ib2c8c57020405bcd14070dcd7bc71cbfe18230e3
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-13 17:04:08 +08:00
Elaine Zhang
5694edffc8 clk: rockchip: rk3399: fix up some regs description error 
Change-Id: Ia992b20f13ba7037b93fcd2fbd67a4d6b3fd1266
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-13 17:04:08 +08:00
Finley Xiao
88a0aa8360 clk: rockchip: px30: Add div50 clocks for sdmmc, emmc, sdio and nandc 
Change-Id: I45d06b01b05afbe14a4a8b86e7abec7a6f25e267
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-13 17:04:08 +08:00
Finley Xiao
c9c50ac217 clk: rockchip: half-divider: Use maximal and best divider 
The bigger the divider, the better the clock jitter.

Change-Id: I4b4e06c71c2f0bdb0e32422fb42c8d490c3ec4bd
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-13 17:04:08 +08:00
Finley Xiao
81b4efc31c clk: rockchip: half-divider: Fix error value when bestdiv is zero 
Zero is a valid value for half-divider.

Change-Id: I23aa8afcd391da95396e5d808c3c424f993c66e3
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-13 17:04:08 +08:00
Finley Xiao
c9ff2db8ab clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-type 
The div offset of some clocks are different from their mux offset
and the COMPOSITE clock-type require that div and mux offset are
the same, so add a new COMPOSITE_DIV_OFFSET clock-type to handle that.

Change-Id: I7d541e29328f37d2ad806b3b6e5ab35b5513b345
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-13 17:04:08 +08:00
Finley Xiao
118ff760f9 clk: rockchip: Fix rk3036 pll rate overflow calculation on 32-bit 
Change-Id: I4e367893e97828b01b3e6ec457714c722d2c0af6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-13 17:04:08 +08:00
Elaine Zhang
99fefcf08f clk: rockchip: rk3288: fix up the 594M pll vco 
Modify VCO within safe limits(600M-3200M).
mark refdiv = 1

Change-Id: I76b69091ee1ff9a0d88f17a1e4dabda6e267caad
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-13 17:04:08 +08:00
Elaine Zhang
5c41d5772e clk: rockchip: fix up the frac clk get rate error 
support fractional divider with only one level parent clock

Change-Id: I6593f908edf4454ef03255080bf9ac1d72c6f64e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-03-13 17:04:08 +08:00