With the earlier patch in this series, all devices that deferred probe
due to fw_devlink_pause() will have their probes delayed till the
deferred probe thread is kicked off during late_initcall. This will also
affect all their consumers.
This delayed probing in unnecessary. So this patch just keeps track of
the devices that had their probe deferred due to fw_devlink_pause() and
attempts to probe them once during fw_devlink_resume().
Change-Id: Id92b3a5d867b5fa8c07c4c40e810928a9631bf9e
Fixes: 716a7a2596 ("driver core: fw_devlink: Add support for batching fwnode parsing")
Signed-off-by: Saravana Kannan <saravanak@google.com>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200701194259.3337652-4-saravanak@google.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from commit 2451e74647)
This reverts commit f9cb1a06e3.
Replaced by commit 54b41388f5 ("ANDROID: vfs: add d_canonical_path for stacked filesystem support")
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Arch timer stops during system suspend. Add arm,no-tick-in-suspend
property in timer.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I24ebe7e027593cfbdbfc5476f196425df640e8d7
HDMI status maybe incorrect in the following condition:
HDMI plug in -> system sleep -> HDMI plug out -> system wake up.
At this time, cat /sys/class/drm/card 0-HDMI-A-1/status is connected.
There is no hpd interrupt, because HDMI is powerdown during suspend.
So we need check the current HDMI status in this case.
Test on rk3288 & rk3399.
Change-Id: I2fbafd1d80b59628bca65e9e45760a24d1668241
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Check the phy status after deassert phy reset for USB 3.0
mode, and wait at most 1ms for phy ready. If wait for phy
status ready timeout, just print warning log and continue
phy init for the time being.
Change-Id: I2677679a99153cf9ee0a043ab6cfb56d9e8dfdf2
Signed-off-by: William Wu <william.wu@rock-chips.com>
dclk_div2 and dclk_div2_phase are undocumented in TRM, but
these two bit should be set at YUV420 output mode.
Change-Id: I711336798a7d352c8f7a85f1fedfa5933d8261ec
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
1.Change to use RK MTD vendor operation
2.RK MTD vendor is incompatible with RK vendor
Change-Id: I7c233b0b0a98c5e93d0722956809a9d6c01663a1
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
After changing the drive strength, fix the current
delayline.
Change-Id: I2aca4ddef692214a9c2e2cf7bae261cea04027b1
Signed-off-by: David Wu <david.wu@rock-chips.com>
We let phy-supply regulator always on to support all usb host port.
For dwc3 host port, which only works at high speed, combphy1_usq
should be deleted at dwc3 node and add 'rockchip,dis-u3otg1-port'
attribute.
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: I3623de2f76ee27ea34fe2a94481319a3ccb7b23b
ACLK_VOP is assigned by cru now.
This reverts commit de0105f86b.
Change-Id: I9b9390c444d215eaf940053d8617f28b3632e6a9
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
The default autosuspend delay of PM runtime is 5000ms,
it's too long. For Rockchip DWC3 controller, if it supports
PM runtime management, e.g. RK3568 OTG port, then we expect
to put the DWC3 controller in runtime suspend at the end of
probe as soon as possible. This can fix the issue that race
condition between power down the DWC3 in runtime suspend and
access the DWC3 in dwc3_gadget_pullup() by userspace.
This patch uses pm_runtime_put_sync_suspend() instead of
pm_runtime_put if enable PM runtime. And according to the
commit f2a2b34e45 ("usb: dwc3: rockchip: use async_schedule
for initial dwc3"), we do pm_runtime_put_sync_suspend() in
async schedule to avoid increasing the boot time.
Change-Id: I378e57d272382d444f1ac52ea2961736e472e713
Signed-off-by: William Wu <william.wu@rock-chips.com>
Lcd and touch use same power, so we must open uboot logo, turn on power
before touch init. When device enter suspend, power will be hold until
touch suspend.
Signed-off-by: Jason Song <sxj@rock-chips.com>
Change-Id: Ifae24073e982bec9d8cd1f1150c2e18c395930e4
Tips: The sel val read via VAL0_BASE VAL1_BASE VAL2_BASE.
Change-Id: Ida4eee44f4e4cd6a51ca81eeb28e39091433edf2
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
