Call the clock's round_rate op, if it exists, before setting
dvfs rate. Ensures dvfs is set to the rate the clock will
be at after the later call to set_rate.
Change-Id: I4c8e85991238492adc3c37aed57c7269f3b41a2c
Signed-off-by: Colin Cross <ccross@android.com>
A struct nvmap_handle may be shared by multiple clients. If the
original client (the handle "owner") is destroyed, but the handle is
still referenced by other clients, h->owner points to freed memory. To
prevent this, clear h->owner when the owner frees its reference to that
struct nvmap_handle.
Change-Id: I54722091568ce2058f5988e5f6e00e68605a8100
Signed-off-by: Rebecca Schultz Zavin <rebecca@android.com>
Fix the way the total number of carveout allocations is
managed per client.
Change-Id: I3e12e2a98a74cafc1f4c51a48e3c3c549e930160
Signed-off-by: Rebecca Schultz Zavin <rebecca@android.com>
-- release can take a long time
Releasing the out file handles can take a long time, because
we wait for a stop completion that may never arrive.
-- fix possible dma list corruption
If things have gone wrong and a "wait_till_stopped()" times
out, prevent list corrption in the DMA by dequeing any
queued requests.
Signed-off-by: Iliyan Malchev <malchev@google.com>
Added syncpoints reset to host initialization, to synchronize h/w state
with shadow variables.
Change-Id: Ia0a3a644dc5b30ef98158906bcc96954d1c613ff
Author: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Added nvhost device resume function, and moved syncpoints restoration
here from run-time power_host() control. Respectively added syncpoints
saving to nvhost suspend procedure. This change is required, since
power_host() has no way to account for display advancing syncpoints
after they have been already saved.
Change-Id: I2b5452dd4512c7ea16532d28a2d2894ab88929ca
Author: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Fixed a possible null pointer exception when an endpoint gets
disabled while a request is being enqueued in parallel.
Unmap the request buffer if we fail to enqueue the request.
Change-Id: If94cc278c2e6ab58adcf170511e676348365f3f9
Signed-off-by: Benoit Goby <benoit@android.com>
-- Leave I2S running during underflow, for a couple of reasons.
First, the I2S buffers a few samples, and if we get a new write
before those samples are flushed, we will keep continuous audio
Second, we burn CPU time stopping and restarting the HW
frequently.
-- Fix TEGRA_AUDIO_IN/OUT_GET/SET_NUM_BUFS, was causing DMA to
read/write to null HW address.
Signed-off-by: Iliyan Malchev <malchev@google.com>
"Interrupt during enqueue" happens periodically when the
DMA is almost starving. This happens under certain not-
uncommon scenarios.
Signed-off-by: Iliyan Malchev <malchev@google.com>
The previous version of dvfs handled requirements between two
different voltage rails by using two sets of dvfs tables, one
for each rail. That method fails for vdd_aon, which must be
within 170 mV of vdd_core.
Instead, have each dvfs clock only set the voltage rail that
it directly depends on, and add a relationship system to the
voltage rails. When the voltage changes on one rail, it calls
update on all the rails that depend on it. The dependent rails
compare the new voltage of the original rail to their own
voltage, and update their own voltage as necessary.
Change-Id: I17b30a61c7c0c01e44702ab486238789abd47330
Signed-off-by: Colin Cross <ccross@android.com>
Write a dummy value to EMC_MRW_0 to allow
clock frequency changes after lp0.
Change-Id: I2218967eaf9698eef6dcfe2e3edd89fbce2ebf1a
Signed-off-by: James Wylder <james.wylder@motorola.com>
Definitions for 11.2896MHz and 12.288MHz were incorrect. These
frequencies can be still requested through pll_a_out0.
Signed-off-by: Iliyan Malchev <malchev@google.com>
The 608 MHz table entry would incorrectly produce a 760 MHz
clock for input clocks of 12 MHz, 13 MHz, or 26 MHz.
Change-Id: I6755fdde88f0851770490818dc2e5e1e2d512f20
Signed-off-by: Colin Cross <ccross@android.com>
Fuses must be initialized before clocks, so clocks can
determine the maximum cpu frequency. Clocks must be
initialized before DMA, so DMA can enable the clock.
Once DMA is initialized, all fuses accesses must go
through DMA to avoid a hardware bug.
Change-Id: Id1f58e4f43152ec19000e02f2d1ea45abf141f9c
Signed-off-by: Colin Cross <ccross@android.com>
There is a dependency loop between fuses, clocks, and APBDMA.
If dma is enabled, fuse reads must go through APBDMA to avoid
corruption due to a hw bug. APBDMA requires a clock to be
enabled. Clocks must read a fuse to determine allowable cpu
frequencies.
Separate out the fuse DMA initialization, and allow the fuse
read and write functions to be called without using DMA before
the DMA initialization has been completed. Access to the fuses
before APBDMA is initialized won't hit the hardware bug because
nothing else can be using DMA.
Change-Id: Ib5cb0f346488f2869e8314c5f3b24fd86873f4c3
Signed-off-by: Colin Cross <ccross@android.com>
Protect suspend/resume functions behind #ifdef CONFIG_PM. This
prevents a compile error with CONFIG_PM turned off.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Colin Cross <ccross@android.com>
Protect irq suspend/resume functions behind #ifdef CONFIG_PM.
This prevents a link error if CONFIG_PM is turned off.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Colin Cross <ccross@android.com>
Protect the bus suspend/resume functions behind #ifdef CONFIG_PM.
This prevents a compile error if CONFIG_PM is turned off.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Colin Cross <ccross@android.com>
tegra2 hangs if fuse registers are accessed during an apb dma
operation. war is to use apb dma to read/write fuse registers
instead.
Change-Id: I4d99a1ad56115c0d73e9cd0679cf38f70f922f3d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
-- Add support for contnuous single-buffered DMA
-- Remove PIO support
-- Added suspend and resume functionality
Signed-off-by: Scott Peterson <speterson@nvidia.com>
Signed-off-by: Iliyan Malchev <malchev@google.com>
