KBASE_PM_RUNTIME was originally defined by ARM.
However, in the modification to upgrade driver to g29p0-00eac0 (r54), ARM removed KBASE_PM_RUNTIME,
and the source code that depended on KBASE_PM_RUNTIME was modified to be enabled by default.
This modification corresponds to
commit fb91362a23 ("MALI: valhall: upgrade DDK to g29p0-00eac0, from g28p0-00eac0").
Some code previously added by finley.xiao@rock-chips.com also depends on KBASE_PM_RUNTIME.
After picking the above commit, the definition of KBASE_PM_RUNTIME was removed,
making the code added by Finley unable to be enabled.
This may lead to anomalies such as "failed to get ack on domain 'gpu'...",
as referenced in https://redmine.rock-chips.com/issues/568204.
This modification fixes the issue above.
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
Change-Id: Ibf57f363f4f779eceb0e7891271e41cae1a560ea
In some scenarios with high timing requirements, frequent calls to
dma_alloc_coherent may trigger memory reclamation with low probability,
thereby increasing the overall time consumption per frame.
Change-Id: I28ffe47c5db40c82a54254b056f117931efbe38e
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
The iommu device needs to be mapped using a unified main device.
Change-Id: I5b5820b590101dde1713889c056edc034d7322ea
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Reset the RC/EP controller by calling the pm_for_user interface of
the RK PCIe extension.
Change-Id: I6da956f4287017f50a27ad3e0dbb4f0235e981ac
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Fixes: dbcc3c130c ("drm/rockchip: dw_hdmi: Do not enable DSC when the DSC compression ratio is below 0.375.")
Change-Id: Ib94677b9e0588a944feb5e5506eaa9dcbf96bf35
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Auto-Calculation mode Allows IPI frames to change dynamically with the controller
adapting the output frames in vrr mode.
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: Ibcdc520db4b5546ca5877eb02145a5fac7ab7a2c
Sometimes we want to disable the writeback function, which can be
achieved by adding the following configuration at the DTS:
&vop {
rockchip,disable-writeback;
};
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I221f6cb801c46392a545d3d37d9c27ed985d1679
Set debugger irq to IRQF_NO_THREAD, or irq handler calls get_irq_regs(),
and return null.
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: Ic61d2bb2d233e74a2028405b80075eefabd0a9a1
The rk3576 dp port max output height value is the same as vop port.
The detail config value as follow:
DP0 is the same as VP0, set the max output height as 4096;
DP1 is the same as VP1, set the max output height as 2560;
DP2 is the same as VP2, set the max output height as 1920;
Change-Id: Ie96cd8aba47ff5f4070ea902abd535a70e5608b4
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Avoid print the unexpected info when a hpd irq come but
this irq is not for phy test.
Change-Id: Ia61b0cb7494df2ac7c9756ffbf78b1f9d36412b4
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Through analysis of the code logic, we found that the flag
&vop->is_iommu_needed is redundant. After removing it, the iommu
will be enabled at the same time as the first atomic flush operation,
which may refresh the frame or not.
This modification can make codes more concise and allow iommu to be
initialized at an earlier time point, which may avoid the potential
problems(see commit 97e3aa256f ("drm/rockchip: vop2: Remove the
flag &vop2->is_iommu_needed"))
Change-Id: If8932de972c2a4bbd04ac6b3d6c8d363a3b2cefc
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
With CMDQ enabled, issuing a DCMD as the last command before disabling
CMDQ causes the eMMC controller to auto-gate its internal clock. The
state machine mismatch after exiting CMDQ mode triggers data-timeout
errors on all subsequent reads and writes, so the auto-clock-gate
function must be disabled whenever CMDQ is enabled.
log:
mmc2: Timeout waiting for hardware interrupt.
mmc2: sdhci: ============ SDHCI REGISTER DUMP ===========
mmc2: sdhci: Sys addr: 0x00000001 | Version: 0x00000005
mmc2: sdhci: Blk size: 0x00007200 | Blk cnt: 0x00000000
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Ibafa74fc2db29b841b5b4df21ef484478f96a44e
Now the PCIe stack doesn't allow more than one root port to share
the same domain. So assign pcie1's domain to one to fix the failure.
[ 3.172125] sd 0:0:0:2: [sdc] Attached SCSI disk
[ 3.174805] sda: sda1 sda2 sda3 sda4 sda5 sda6 sda7 sda8
[ 3.175709] sd 0:0:0:0: [sda] Attached SCSI disk
[ 3.175742] rk-pcie 2a210000.pcie: PCIe Link up, LTSSM is 0x130011
[ 3.175759] rk-pcie 2a210000.pcie: PCIe Gen.2 x1 link up
[ 3.175797] rk-pcie 2a210000.pcie: Scanning root bridge failed
[ 3.175812] rk-pcie 2a210000.pcie: failed to initialize host
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: If933fb89d663e8c2b1337cd5886af9f730697ec1
If a new wb commit is too close to the timing of wb dma complete,
clearing the wb intr status will lose the wb dma complete status.
In this case, the software process is as follows:
vop_wb_commit() -> vop_wb_irqs_enable() -> Clear wb intr ->
vop_isr() -> vop_read_and_clear_wb_irqs()
Since we had cleared the intr in vop_wb_irqs_enable(), the value read
by vop_read_and_clear_wb_irqs() is 0, and we have lost the interrupt
status.
Change-Id: Ida08e94ce1d987f7edbcb6448c0b3f034add1bce
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
