When conducting FRL training, the video data transmitted from
VOP to HDMI must be disabled. Until the training is successful
or fails, then it will be reopened. When the FRL training fails,
the video transmission from the video to HDMI is not re-enabled.
This will result in the inability to display normally even when
switching to tmds mode after training fails.
Therefore, regardless of the specific scenario, when switching
to the tmds mode, the data transmission from VOP to HDMI must be
enabled.
Change-Id: I1c853c8197fdf7aaef32c80c5cdb73db13d9ec4c
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
The variable 'T' in the calculation formula
'output = T * M1 * N_y2r * M0 * N_r2y' has been omitted.
Change-Id: I347eca9786729de0ce35c35f483b55a7cb62bd7e
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
In analogix_dp_link_start(), &link_train.training_lane[] is used to
set phy PE/VS configurations, and buf[] is initialized with the same
values to set DPCD DP_TRAINING_LANEx_SET.
It makes sense to reuse &link_train.training_lane[] to set DPCD
DP_TRAINING_LANEx_SET, which can remove the redundant assignments
and make codes more consice.
Change-Id: I38869c22f8cc93b18b3b27bc41a0975700b328d1
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
KBASE_PM_RUNTIME was originally defined by ARM.
However, in the modification to upgrade driver to g29p0-00eac0 (r54), ARM removed KBASE_PM_RUNTIME,
and the source code that depended on KBASE_PM_RUNTIME was modified to be enabled by default.
This modification corresponds to
commit fb91362a23 ("MALI: valhall: upgrade DDK to g29p0-00eac0, from g28p0-00eac0").
Some code previously added by finley.xiao@rock-chips.com also depends on KBASE_PM_RUNTIME.
After picking the above commit, the definition of KBASE_PM_RUNTIME was removed,
making the code added by Finley unable to be enabled.
This may lead to anomalies such as "failed to get ack on domain 'gpu'...",
as referenced in https://redmine.rock-chips.com/issues/568204.
This modification fixes the issue above.
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
Change-Id: Ibf57f363f4f779eceb0e7891271e41cae1a560ea
In some scenarios with high timing requirements, frequent calls to
dma_alloc_coherent may trigger memory reclamation with low probability,
thereby increasing the overall time consumption per frame.
Change-Id: I28ffe47c5db40c82a54254b056f117931efbe38e
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
The iommu device needs to be mapped using a unified main device.
Change-Id: I5b5820b590101dde1713889c056edc034d7322ea
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Reset the RC/EP controller by calling the pm_for_user interface of
the RK PCIe extension.
Change-Id: I6da956f4287017f50a27ad3e0dbb4f0235e981ac
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Fixes: dbcc3c130c ("drm/rockchip: dw_hdmi: Do not enable DSC when the DSC compression ratio is below 0.375.")
Change-Id: Ib94677b9e0588a944feb5e5506eaa9dcbf96bf35
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Auto-Calculation mode Allows IPI frames to change dynamically with the controller
adapting the output frames in vrr mode.
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: Ibcdc520db4b5546ca5877eb02145a5fac7ab7a2c
Sometimes we want to disable the writeback function, which can be
achieved by adding the following configuration at the DTS:
&vop {
rockchip,disable-writeback;
};
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I221f6cb801c46392a545d3d37d9c27ed985d1679
