There is one wmb missing in the usb host controller driver after the queue head
update. Due to this data transaction is not happening on the bus after urb
submission by the hcd driver. Register updates/queue heads data in the memory
is not reflected on the AHB bus. After adding the wmb after queue head update
data transaction the USB bus started with out any delay.
originally fixed by Venkat Moganty <vmoganty@nvidia.com>
Change-Id: Ic834df5172ac2f2eb3bced317d38b4a2e7a44801
Signed-off-by: Jay Cheng <jacheng@nvidia.com>
The regulator framework may need to change certain regulators when
entering suspend.
Change-Id: I584e92b3c32cbd1a63325831822e2704a3dd2774
Signed-off-by: Greg Meiste <w30289@motorola.com>
The hdmi block contains a divider that is not visible to the clock
subsystem, prevent auto dvfs on it so that clk_set_rate can set the
input clock higher than 148.5 MHz.
Change-Id: I7f09f4d099e2f24166a65b1b582fe16c1451deba
Signed-off-by: Colin Cross <ccross@android.com>
* read blocks in a single command instead of byte at a time
* allow reading past segment 0 (edid > 256 bytes)
* handle mutiple extention blocks
* add debugfs file for reading edid
Change-Id: Iec8182cdbccdaa2142e4bbc892202d2e8d73c23b
Signed-off-by: Erik Gilling <konkers@android.com>
The PLLP registers are now being restored by the low-level resume code,
and the CPU may be running off PLLP, so don't touch them during clock
resume.
Change-Id: Ida248a929c8b59f2e51f43dbbef1cd792ef68737
Signed-off-by: Colin Cross <ccross@android.com>
Save and restore the PLLP registers in the platform suspend code, as
the CPU clock may be sourced from the PLLP registers later, before
the clock resume that used to re-enable PLLP has been called.
Change-Id: I0ffc18d8a7f2d62c544328bd44ca7cf62848bc44
Signed-off-by: Colin Cross <ccross@android.com>
In LP1 suspend, or during a failed LP0 suspend, the core power is
not turned off and the timer register is not reset. Saving the
timer value during suspend and adding it to the offset after resume
will cause the timer value to double for each suspend cycle.
To fix, when resuming subtract the current value of the timer
register from the offset. Also, use the rtc registers to add
the time that passed during suspend.
Change-Id: I9f7ee2089b98cf66af45271f8478fbd9eb2ee250
Signed-off-by: Colin Cross <ccross@android.com>
The 32k clocksource is never used, because it is always registered
at the same time as the us clocksource, which has a higher rating.
Using the 32k clocksource would cause a race condition with the
tegra_rtc driver on the RTC shadow registers. Remove the 32k
clocksource, add a replacement tegra_read_rtc_ms function for the
suspend code to track suspend time, and add a comment on
read_persistent_clock that it should never be called while the
tegra_rtc driver is running. It is currently only called from
timekeeping init, suspend, and resume.
Change-Id: Ic964578e9923b0f0338959f75de1ac170f850337
Signed-off-by: Colin Cross <ccross@android.com>
Turn on the cpuidle_device power_specified field
to enable usage of the defined cpuidle_state.power_usage fields
for each state.
Signed-off-by: James Wylder <james.wylder@motorola.com>
Change-Id: Ibca20a937bf4079f61e4b3ae64394d797b4eb287
Signed-off-by: Todd Poynor <toddpoynor@google.com>
Some peripheral clocks share enable bits. Refcount the enables so
that calling clk_disable on one clock will not turn off another
clock.
Change-Id: Iefb015bc83cac77b3faef8db86cfc42b25c0b6ae
Signed-off-by: Colin Cross <ccross@android.com>
New and improved dvfs:
Registered dynamically during init
Exports dvfs functions to control clocks that are not visible to
the clock subsystem
Supports multiple regulators per clock
Fix dvfs on disabled clocks
Adds /d/clock/dvfs to show current voltage requirements
Change-Id: I93794a7761dccc702566e8850bb79f344ff787a2
Signed-off-by: Colin Cross <ccross@android.com>
During cpu frequency changes, take an extra reference to pllx so
that it doesn't turn off and on while the cpu is on pllp.
Change-Id: I574d399a67aab21f99473296a29aa1eedc0eedb9
Signed-off-by: Colin Cross <ccross@android.com>
The PLL lock bits are not reliable, use per-PLL timeouts instead.
Change-Id: I2749e0d8bcfb0b60dbbcf6378b38307f77ff8d4d
Signed-off-by: Colin Cross <ccross@android.com>
Move dc init to the device init level so that all clocks are
initialized before the late init level. This depends on I2C
being initialized in the subsys init level.
Change-Id: Iafe759d943b6cc90d5c6718b69e872e14d6acd4e
Signed-off-by: Colin Cross <ccross@android.com>
Some drivers (like hdmi) need to communicate over i2c during probe.
Move the i2c bus init to the subsys init level so that i2c is ready
for the start of the device init level.
Change-Id: I81234d42aa26b657ffc619099e47df09e12083bb
Signed-off-by: Colin Cross <ccross@android.com>
