The RK3568 has two gmac, but the driver only support one mac address
right now, define the more ethernet mac address at vendor storage to
support it.
Change-Id: If47df961136da6fe13ede1e5817717db2c0ad2f6
Signed-off-by: David Wu <david.wu@rock-chips.com>
Add constants and callback functions for the dwmac on RK3568 soc.
As can be seen, the base structure is the same, only registers
and the bits in them moved slightly.
Because there are two gmac controllers at rk3568, use
bus id to set the corresponding registers respectively.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I26e8dbc172c7c14df230f531251e2cd23d78a787
Add constants and callback functions for the dwmac on RV1126 soc.
As can be seen, the base structure is the same, only registers
and the bits in them moved slightly.
Because the gmac driver does not know whether pinctrl is
configured with m0 or m1 at this time, so we configure the
delayline of m0 and m1 at the same time.
Change-Id: I3bf58f30584f91c53dd98f747b2d5a2e3f32c505
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Use the phy_clk to prepare_enable and unprepare_disable related phy clock.
Change-Id: Idcf3ee00c03b4a5009a6a9385077b0a421dbc601
Signed-off-by: David Wu <david.wu@rock-chips.com>
The gmac5.10a configure has_gmac4 with true and has_gmac with false.
Others still stay has_gmac with true.
Change-Id: I0d0d1adef8551d2f7aac6702f963cb23a9861036
Signed-off-by: David Wu <david.wu@rock-chips.com>
Add constants and callback functions for the dwmac on rk1808 soc.
As can be seen, the base structure is the same, only registers
and the bits in them moved slightly.
Change-Id: I39a75b89cd17331bb4373b9b249ae206e1420e71
Signed-off-by: David Wu <david.wu@rock-chips.com>
Add constants and callback functions for the dwmac on rk3308 soc.
The base structure is the same, but registers and the bits in
them moved slightly, and add the clk_mac_speed for the select
of mac speed.
Change-Id: Ieaea3ade9e51d5118f0eb855d8e02febfb2275d1
Signed-off-by: David Wu <david.wu@rock-chips.com>
The MDC clock is divider from APB Clock for rockchip's socs, if it
was from mac_clk, the mdc clk range might not be between the frequency
range 1.0 MHz - 2.5 MHz.
Change-Id: I4e4fcb1be239a8d78a39fc1f4e2af5bb87258798
Signed-off-by: David Wu <david.wu@rock-chips.com>
This reverts commit f19114808f.
devinfo is unused.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I177ecd227330250bb33fc350cbe850a8cca5a751
because currently mclk is handled by codec side, so the
associated pinctrl should be handled by codec too.
Change-Id: I55db6e9a0181cae0cb414b9dcacae7ff0214b50c
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
The cpufreq cooling doesn't support calculating static power in 5.10
and the cpu and gpu opp table are changed.
Change-Id: Ia1abaf6d7614b874081159db7cc41e910bf47462
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Commit af02b05e59 ("mmc: add thunder boot support")
add this function wrong. So just remove it.
Fixes: af02b05e59 ("mmc: add thunder boot support")
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I9177c615163826e3df2ba692e63f9aadf48ef912
The power model node must be the child node of the device node.
Change-Id: Ib16e37c31e573f183ea304b072d2a7912e155197
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
to modify bus width error sometime plug out hdmi and switch cvbs output
Change-Id: Iaa7914fbccc99991fbfbc5495ba647f97997c8ba
Signed-off-by: Huicong Xu <xhc@rock-chips.com>
If HDMI output corlor mode is YCbCr422, the tmds clock is same
to YCbCr444 8bit, phy bus width should be set to 8.
Change-Id: I6e844e676a6315ae0cb88b0bd8456f0e27fa5e0c
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
1.Filling the HDMI AVI infoframe quantization range information.
2.If output is limited enable color space conversion to convert.
Change-Id: I75f666424f00f3f6ec695047f7851824e89cd1a5
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Under the following conditions, phy will be abnormally enabled.
1. HDMI is enabled in uboot.
2. disabled/bridge_is_on/phy.enabled/mc_clkdis were updated to
work when probe.
3. HDMI is disconnected.
4. drm_helper_probe_single_connector_modes update connector->status
to disconnected and power off phy by dw_hdmi_update_power. But the
polled type of HDMI is DRM_CONNECTOR_POLL_HPD, output_poll_execute
will not process this disconnection, and dw_hdmi_bridge_disable is
not called, hdmi->disabled is still false.
5. vop will be switch to Tv encoder, and dclk is 27MHz.
6. HDMI is connected.
7. dw_hdmi_update_power is called in dw_hdmi_irq, for hdmi->disabled
is false, then phy is powered up with parameter of 27MHz, and
bridge_is_on is set to on.
8. VOP switch to HDMI mode, set the new dclk rate.
9. dw_hdmi_bridge_enable is called, but the bridge_is_on is already on,
phy will not set again, still maintain the parameters that do not
conform to the new dclk rate.
This patch introduced an variable initialized to indicate hdmi is
initialized before probe, e.g. uboot. When power off hdmi, initialized
and disabled is updated.
Change-Id: I163967ac02e7f29ab586acbfd25d5a15679470c8
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Include the following commit:
1.update mc_clkdis in dw_hdmi_bind.
2.update more hdmi status in dw_hdmi_bind.
3.Fix hdmi can't display in android.
4.Update criteria to determine whether uboot logo is on.
5.disable phy in dw_hdmi_bind.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I4d1269062b0a4c01d0e82923bf9bb6dad3411387
Switch is no longer available in kernel 4.19, so
we use extcon instead.
the hdmi connect status node:
/sys/class/extcon/extconX/state
HDMI=0:
hdmi is disconnected
HDMI=1:
hdmi is connected
Change-Id: I806d8fd5b9b4b36f15aa6aec275fad2ecf122e91
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
1.change SDA high level holding time to 3us.
2.when plug in,add timer to avoid unstable state.
Change-Id: Idc6faec710137ac9f8e589d75cbc1b85f7a45faf
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Serial Flash controller is used to control the data
transfer between this SoC and a serial nor or nand
flash device.
Change-Id: Ibe7c8c4a11410287c34c1a7dc5b232b330ee6751
Signed-off-by: Randy Li <randy.li@rock-chips.com>
The vpu qos registers need to save and restore when reset.
Change-Id: I649cf4a360842ad1abb06c35a6fd8d3868fbf706
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
According to the actual schematic designed by kylin board, update and
rename the regulators for rk808 node information.
Especially gpu regulator voltage, the schematic didn't have this
regulator, this regulaor should be applied by cpu regulator since the
cpu/gpu/ddr are belong to the same logic power supply.
Change-Id: I39e4cf18969391da396cc775f8660701e42977bd
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
As the vpu needed handle the power domain for reset function, this patch
supported the vpu domain for rk3036 Socs.
Change-Id: I67ad6085e2eb9a213c364d58713f02cc78ce6849
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
rk3036 doesn't support vdd_arm power supply off when system suspend.
Change-Id: I46bd8a7c2b672be30d8106b867275e8ba7d77e54
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
As the HDMI-audio/codec will cause the hang on bootup, the root
cause that kylin get the invalid master clock from i2s.
$cat/sys/kernel/debug/clk/clk_summary
..
i2s_pre 0 0 0 0 0
sclk_i2s 0 0 0 0 0
i2s_clkout 0 0 0 0 0
Since i2s clock selects io input clock by default, but the hardware
didn't supply the clock.
This patch will fix the sclk_i2s's parent on i2s_frac.
As following:
$cat/sys/kernel/debug/clk/clk_summary
..
i2s_src 1 1 594000000 0 0
i2s_frac 1 1 22579200 0 0
i2s_pre 2 2 22579200 0 0
sclk_i2s 1 1 22579200 0 0
As far, the audio can work with aplay/record on kylin.dts
Says:
(aplay /dev/urandom)
/* recording */
arecord -f cd -d 10 /tmp/audio.wav
/* playback */
aplay /tmp/audio.wav
Change-Id: I73534a0d763eb02fb55e000ce068d9d604bf20ed
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
As the cpu frequency is less than 816MHz, the HDMI display maybe
probably cause a flower screen as below log[0]. And Kylin used the rk3036g
series SoCs that the max cpu frequency supported the 1GHz, not 1.2GHz.
In a word, keep the cpu frequency to 1GHz for kylin board.
log[0]:
[26.498843] rk_iommu 10118300.iommu: Enable stall request timed out,
status: 0x000011
[26.528809] rk_iommu 10118300.iommu: Disable paging request timed out,
status: 0x000011
[26.598849] rk_iommu 10118300.iommu: Enable stall request timed out,
status: 0x000011
[26.607579] rockchip-vop 10118000.vop: Failed to attach iommu device
[26.614916] rockchip-vop 10118000.vop: failed to attach dma mapping, -110
..
Change-Id: I8e1d4527b649d8857a9d80a121c10935a4cd1030
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
As the emmc is supplyed power by vcc_io, that's 3.3v voltage.
the default 1.8v volatge will cause the emmc error. as the following:
[ 17.096082 ] mmcblk1: error -115 sending stop command, original cmd
response 0x900, card status 0xb00
[ 17.127022 ] mmcblk1: error -110 transferring data, sector 664720, nr
72, cmd response 0x900, card status 0xb00
Remove the mmc-ddr-1_8v to keep the default the 3.3v voltage.
Change-Id: I9e2539d63fd93e72d9febbb311fbd686c5a11d09
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This patch supported the gpu opp table for rk3036.
The gpu clock's parent is DPLL, the default frequency is 400MHz, we need
assign 400MHz for gpu to be better working.
There is a quickly way for testing the gpu scaling frequency.
As following:
"
unset FREQS
read -a FREQS < /sys/class/devfreq/10091000.gpu/available_frequencies
RANDOM=$$$(date +%s)
while true; do
echo userspace > /sys/class/devfreq/10091000.gpu/governor
FREQ=${FREQS[$RANDOM % ${#FREQS[@]} ]}
echo GPU:Now ${FREQ}
echo ${FREQ} > /sys/class/devfreq/10091000.gpu/userspace/set_freq
sleep 1
done
"
Change-Id: Ia8eb3074e457014c497338a0a129551c51450104
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This patch supported the cpu voltage by changed with different
frequency, otherwise we will hit the following error on bootup.
..
[ 5.031516] cpu cpu0: Failed to get cpu_reg
[ 5.047725] cpu cpu0: clk or regulater is unavailable
..
Also, remove the 408M and 600M for rk3036 board, as the pclk_hdmi's parent
on apll, the low frequency will make the pclk be bad for hdmi display.
Change-Id: Ia4aac76a08cad3a59c33cd81065f943201a23a35
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This patch fixes the BT power reported the failure message.
As following:
root@linaro-alip:~# echo 1 > /sys/class/rfkill/rfkill0/state
[ 892.558269] rockchip-pinctrl pinctrl: pin gpio0-19 already requested
by 20060000.serial; cannot claim for wireless-bluetooth
[ 892.571052] rockchip-pinctrl pinctrl: pin-19 (wireless-bluetooth) status -22
...
And for now, the BT can work with this patch.
root@linaro-alip:~# echo 1 > /sys/class/rfkill/rfkill0/state
[ 69.328768] [BT_RFKILL]: ENABLE UART_RTS
[ 69.438540] [BT_RFKILL]: DISABLE UART_RTS
[ 69.443117] [BT_RFKILL]: bt turn on power
...
root@linaro-alip:~# hcitool dev
Devices:
hci0 94:A1:A2:E9:2D:18
And
root@linaro-alip:~# bluetoothctl
[NEW] Controller 94:A1:A2:E9:2D:18 linaro-alip [default]
[bluetooth]# scan on
Discovery started
[CHG] Controller 94:A1:A2:E9:2D:18 Discovering: yes
..
Change-Id: I2148f4203300ab4265fd3ba718f0d3ec0c57e7ca
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
It allows me to set the mac address in the bootloader.
Change-Id: Iad988205c6953e843e62aec67daad52128086324
Signed-off-by: Randy Li <randy.li@rock-chips.com>
