rk3328 dwc3 has a problem that USB 2.0 MAC lineState not
reflect the expected line state (J) during transmission.
Add this quirk to add the ipgap between (tkn to tkn/data)
with 40 bit times of TXENDDELAY, and linestate is ignored
during this 40 bit times delay.
Change-Id: I76895476bff94c2198a5d8df7e73b9d54fbb96ed
Signed-off-by: William Wu <william.wu@rock-chips.com>
The USB 3.0 PHY need to config grf when change between
USB 2.0 only and USB 2.0/3.0 mode, so we add grf property
for u3phy node.
Change-Id: I4ff2670d0637e9d0cbae06f5e9efbde9a8513bb3
Signed-off-by: William Wu <wulf@rock-chips.com>
This patch adds a quirk to disable rk3328 xHCI controller
USB3 port autosuspend function, and USB2 port autosuspend
function is still enabled.
Change-Id: Ie5e6883811b09a9a0d839ce59d8f9c4ad8ad3378
Signed-off-by: William Wu <wulf@rock-chips.com>
This patch adds USB 3.0 PHY grf node and apb node
for rk3328 USB 3.0 module.
Change-Id: I9d4e6c6d6792ac5fd6c2a4d7cc902f1ff0cf4ef1
Signed-off-by: William Wu <wulf@rock-chips.com>
This patch doesn't fix any issue, but conforms
to linux coding style.
Change-Id: I87326a21594b905ea5791f73efc1cea0299abe4d
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Rk3399 support single and burst mode, and flushp instruction.
But burst mode improve transfer efficiency.
Please refer to:
Commit 8e770f371c
"dmaengine: pl330: add burst mode according to dts config"
Change-Id: I2eb36723697cf548dc75aca0e5a276a86cd2419d
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
set armclkb 816M to slove the crash,which reset core voltage below 0.85V.
So make sure the 0.8V voltage is enough for the init clk freq.
Change-Id: I4dba25fdfd610c0751f50ce09283c32a9b3f420f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Rockchip RK3399 SoCs support reboot with modes, such as recovery mode,
loader mode and normal mode.
Change-Id: I96ed872f849c2b3b06d236248995db18be070960
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Let's assign clk parent and rate for SCLK_EMMC to meet the
requiremen.
Change-Id: I3730a2124494da51717b1756f488f9df5bcd6423
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
We need to put the power status of HEVC IP into IDLE unless
we can't reset that IP or the SoC would crash down.
rockchip_pmu_idle_request(dev, true)---> enter idle
rockchip_pmu_idle_request(dev, false)---> exit idle
Change-Id: I76733efd2de4f7ee183c1b6bd1545d60038ee31b
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Randy Li <randy.li@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Before reboot if the DCDC is disabled,
the DCDC is still disabled after restart.
We have an method to workaround:
Use vsel pin to switch the voltage between value in FAN53555_VSEL0
and FAN53555_VSEL1. If VSEL pin is inactive, the voltage of DCDC
are controlled by FAN53555_VSEL0, when we pull vsel pin to active,
they would be controlled by FAN53555_VSEL1.
In this case, we can set FAN53555_VSEL1 to disable dcdc,
So we can make vsel pin to active to disable dcdc,
VSEL pin is inactive to enable DCDC.
Change-Id: I14c823ed11dc3369044ad2ed0b53a6027acbccd0
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
It has proved the controller has a potention broken state with a DTO
interrupt comes while the data payload is missing, which was not
covered by current software state machine. Add a xfer timer to work
around this buggy behaviour introduced by broken design.
Change-Id: I5019c5ba0cdeb59adcdd3a5231a2000b448762bc
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Android healthd try to listen power_supply subsystem uevent,
but which will block system from suspend on big.LITTLE system
because thermal_cooling_device_unregister will called when
cpufreq_exit. So ignore this uevent when suspend.
Change-Id: I35948498916560d5ec75fe561c9e9d588663ad22
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
