When hdcp repeater's device count is 0, hdmi controller
will not update bstatus in hdcp1.4 ram. So bstatus should
be read via ddc directly.
Change-Id: I891f3824c0e77586c1180b118d38da4667e4a927
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
HFR1-17 requires that when the frl rate in edid
is protocol undefined, hdmitx must output the
maximum supported frl rate.
Change-Id: I61a0152d570e826207f51724578b0113e8818302
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Added flt state machine thread to ensure that frl cts can pass:
1.Support txFFE Level switch.
2.Support LTS4.
3.Polling sink frl status after flt pass.
Change-Id: I0d2aa1e8fb5ae39ff3493daf4f2036dffe0817a2
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
CONFIG_SND_PCM_PATTERN_DEBUG
* MSB check
* channel id
* as much as more 0/1 stress
PATTERN8(x) (0xa0 | (x))
PATTERN16(x) (0xab00 | (x))
PATTERN32(x) (0xabcabc00 | (x))
e.g. 16bit 4ch pattern:
0xab01 0xab02 0xab03 0xab04 0xab01 ...
This pattern is only used for IOCTL_READ/WRITE, not
suitable for MMAP.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I96d9664460adeee13ac86558159b39c9ab0dabe8
CONFIG_SND_PCM_PATTERN_DEBUG
* MSB check
* channel id
* as much as more 0/1 stress
PATTERN8(x) (0xa0 | (x))
PATTERN16(x) (0xab00 | (x))
PATTERN32(x) (0xabcabc00 | (x))
e.g. 16bit 4ch pattern:
0xab01 0xab02 0xab03 0xab04 0xab01 ...
This pattern is only used for IOCTL_READ/WRITE, not
suitable for MMAP.
Change-Id: Ida01d0e30b20d0a14f3b8439eed430af8a3a9d56
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This commit adds pinctrl idle/clk configuration for the PDM on RK3576 boards to improve power management and reduce clock glitches during runtime.
commit: 48aa220b8b ("ASoC: rockchip: pdm_v2: Fix clk glitch on runtime PM")
Signed-off-by: XiaoTan Luo <lxt@rock-chips.com>
Change-Id: I41ad272a19656af325b42e4284296a21f14cafe4
This adds a standalone driver to support PCIe hotplug functionality
merely based on a GPIO indicating the status of a downstream device
connectivity. It looks for "hotplug-gpios" property in the corresponding
device node to get the GPIO information.
It also provides a mechanism for platform drivers of the controllers
to register ops to perform any platform specific operations while
enabling/disabling the slots.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Link: https://patchwork.kernel.org/project/linux-pci/patch/20220930192747.21471-3-vidyas@nvidia.com/
Change-Id: Iafa798ee4d98f195f5d33d80120da0c569132548
before:
text data bss dec hex filename
4880931 2116804 107272 7105007 6c69ef vmlinux
after:
text data bss dec hex filename
4922448 2288868 118408 7329724 6fd7bc vmlinux
Change-Id: If066c764f6f17c35041f9f6a12afe255334b4f46
Signed-off-by: Lin Jianhua <linjh@rock-chips.com>
When switching sample rates, the clock settings are as follows:
- For 48K, MCLK = 256fs = 256 * 48K = 12288K
- For 16K, MCLK = 256fs = 256 * 16K = 4096K
- For 8K, MCLK = 256fs = 256 * 8K = 2048K
The `set_sysclk` function in the soc i2s_tdm controller does not
actually perform `clk_set_rate`; it merely passes the parameters.
The actual `clk_set_rate` is called during `i2s_tdm_hw_params`.
However, `rk817_hw_params` performs `restart_clk_apll` inside,
which sets the PLL parameters that do not match the MCLK,
resulting in silence. To resolve this, clk_set_rate for the MCLK
frequency should be called within the set_sysclk function.
Signed-off-by: XiaoTan Luo <lxt@rock-chips.com>
Change-Id: I3ad233542a5e8b16ae72f829e086a25f5be4a095
This patch will impact performance, so disable this feature by default.
This reverts commit 980a9f6834.
Change-Id: I8f7e2413049f92e87b4a915e9e597172ecb955ce
Signed-off-by: Liang Chen <cl@rock-chips.com>
According to SPI signal test results:
(1) When using SPI IOs under 3.3V power domain, need to increase
driver strength to level3.
(2) When using SPI IOs under 1.8V power domain, use default driver
strength(level2) is best.
Change-Id: I0404418256d4f9671393345bf44ffd4e285af584
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>
1. Prevent data from crossing boundaries
2. Support GPIO_TYPE_V2_2 debounce config
Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Change-Id: I57e295806a4f0f4002527daf77fe41f584a7e9e1
mclk pin has been addressed in i2s_8ch_mclk, and used by
codec, so, do not redefine it again in i2s_8ch_bus.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I74a3c3f817142ff4c313bbf9a39ced215f04feb6
1.mipi date rate need to set 1850Mbps
2.DSI RGB output need to set skip first frames
Signed-off-by: Jianwei Fan <jianwei.fan@rock-chips.com>
Change-Id: I0a339e339bd94dae66be682a4481a4b0cef8ff99
