Since HDMI needs clock rate 74.25MHz, so plls must support
a multiple of it.
For Rockchip rk3368 pll has better jetter with 1188MHz, so
add 1188MHz support.
Change-Id: I68c7333ae076ecabf8637298ee8ca43149cb17d1
Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>
Add "assigned-clocks" for rk3368 cru node, to intalize
clock rate for plls, bus and peripher.
Change-Id: Ic36401fef73b005d778b8ccc8527633af408985c
Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>
I2S_2CH set freq need to select parent and calculate parent freq.
so just mark it as the CLK_SET_RATE_PARENT flag.
Signed-off-by: zhangqing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.6-clk/next
commit e8099067de)
Change-Id: I1e7b75eba06fbe27079c3887170ce801da005ce0
SPDIF_8CH set freq need to select parent and calculate parent freq.
so just mark it as the CLK_SET_RATE_PARENT flag.
Signed-off-by: zhangqing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.6-clk/next
commit 0bbe62eb92)
Change-Id: I3deed226430c492dc3b70337ae3e89d201aeb66d
The edp_24m parent select bit define is:
1'b0:xin24m
1'b1:1'b0(dummy)
so adapt the parent sel bit to the currect one.
Signed-off-by: zhangqing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.6-clk/next
commit d566ebc3c0)
Change-Id: Ia0530f4e00c8ea15420b49587097f07ac1af5092
The vdpu and vepu clocks can also be parented to the npll and current
parent list also is wrong as it would use the npll as "usbphy" source,
so adapt the parent to the correct one.
Fixes: 3536c97a52 ("clk: rockchip: add rk3368 clock controller")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: zhangqing <zhangqing@rock-chips.com>
Cc: stable@vger.kernel.org
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.6-clk/next
commit 0f28d98463)
Change-Id: Ie7e8f1e7d6de5e149705cc5f6d6207e839eca2bd
Similar to commit 9880d4277f ("clk: rockchip: fix rk3288 cpuclk core
dividers") it seems the cpuclk dividers are one to high on the rk3368
as well.
And again similar to the previous fix, we opt to make the divider list
contain the values to be written to use the same paradigm for them on all
supported socs.
Fixes: 3536c97a52 ("clk: rockchip: add rk3368 clock controller")
Reported-by: Zhang Qing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: zhangqing <zhangqing@rock-chips.com>
Cc: stable@vger.kernel.org
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.6-clk/next
commit c6d5fe2ca8)
Change-Id: If85678467e8dc4b4cfce07c3d31faf0c11479780
Both clusters have their mux bit in bit 7 of their respective register.
For whatever reason the big cluster currently lists bit 15 which is
definitly wrong.
Fixes: 3536c97a52 ("clk: rockchip: add rk3368 clock controller")
Reported-by: Zhang Qing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: zhangqing <zhangqing@rock-chips.com>
Cc: stable@vger.kernel.org
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.6-clk/next
commit 535ebd428a)
Change-Id: I26364fdba8cdfe36c8b9ba767b4226c9ac6ff118
This patchset attempts to new compatible for thermal founding
on RK3228/RK3399 SoCs.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
(cherry picked from git.kernel.org torvalds/linux.git master
commit 4be02530fc)
Change-Id: I9fd1f52d7b4781230e5436e90ed6d9d2c95d06cb
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This patchset trys to dictate unified format for driver.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
(cherry picked from git.kernel.org torvalds/linux.git master
commit 13c1cfda1a)
Change-Id: I9659ae150c9d24f2482fd8c285dcfeb65bf873b1
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Add the devicetree binding for the cru on the rk3366 which quite
similar structured as previous clock controllers.
Change-Id: I109da26f88cd733b64d4c4339db63346dd9ffea6
Signed-off-by: Xiao Feng <xf@rock-chips.com>
Add the dt-bindings header for the rk3366, that gets shared between
the clock controller and the clock references in the dts.
Change-Id: Ie4d8f9d02be2331b368d44f5d76a92fd9959b72a
Signed-off-by: Xiao Feng <xf@rock-chips.com>
Skip the update_reg_update when vop is suspend, because
register access would hang up the system when vop is suspend.
Change-Id: I01e712736df9a6de88440ee67c624a26ea752d85
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Vop hardware only support the 4 byte align stride, but
if logo's stride is not align with 4 byte, will get
error display.
Change-Id: I543bbbea98f14702ae0e5f058075c39b8fd6fd68
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
kernel logo not use ymirror now, so if uboot logo use ymirror,
we need close it when switch to kernel logo, otherwise, would get
iommu crash
Change-Id: I4a607f75ada4cf6454c7e0f4614b629ef747e851
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
if the extend screen type is same to prmry screen type,
the GRF reg config for vop selete will be error;
Change-Id: I6671ae69da175352bd1935254603e434e85900ea
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>
Support cma-heap, also remove unused id definations.
Change-Id: I81608291b076ed55a1c439abfa9281ba30dff1b6
Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>
With the RK3399 FPGA dts file, the FPGA board is able to boot with
very simple boot system.
Change-Id: I3484faf02cf9e6adab4379752abcc6cb8c9ed5b2
Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>
Add the dt-bindings header for the rk3399, that gets shared between
the clock controller and the clock references in the dts.
Change-Id: I01830a46b679f4630506e8cb48b1a39e113a9952
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
RK3228's armclk has 3 parents, so allow cpuclk to have
more than 2 parents.
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from linux-next.git
commit ea03835fb8)
Change-Id: Iddb60e4f7bda91b98b4a3e42f196eee510173dce
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Currently, when tring to set up a serial console with a higher
baud rate, it would fallback to 921600.
Tested-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Change-Id: Id93f2b559478f38c735213d523d3f72f6745f6a0
Direct load 24bit bmp data to display, but its data format
is BGR888, so add BGR888 support for uboot logo.
Change-Id: Id93f2b559478f38c735213d523d3f72f6745f6a8
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Uboot logo need ymirror function, but now only have mirror_en to
enable both xmirror and ymirror.
Change-Id: Ic676c4451817db2127327a1a56addeccb2436f21
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Uboot logo address start point may be not align PAGE_SIZE, it would
align to wrong point by pages vmap, and cause uboot logo error display.
So before pages vmap, align the uboot logo address.
Change-Id: I93f030e1b7ee13a4dc19d1421f520478868318ef
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Reported-by: Wen Dingxian <shawn.wen@rock-chips.com>
We enable win0 for uboot display, but win last_state is 0,
when we update win config from config_done ioctl, the state judge
is wrong.
Change-Id: I9955bed1683586254a908cb9395d27585e234b10
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Now only find rk322x and rk3368 support do ymirror in windows.
Change-Id: Iba49d64bb51db8fb35e6b21cab8aeba23dbd52b6
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
All layers allow out of right side and bottom side.
And hardware cursor want to support outside of right and bottom.
Change-Id: I27d64b2e12326fbad436f291a9fb5092538428f9
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
