Physically contiguous virt_addr needs to add the offset of the first
page when obtaining the phys_addr.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: I8076ad2aac31ad61d8a5e0d4332fe69f702d2adb
When the horizontal input exceeds 2k (here refers to 1996), need to switch
from BI-cubic to BI-linear. When there is an HSD(horizontal scale down),
need to check the horizontal input after the HSD.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: I3e4ceeb0e85811ccb131c22fe77ebaa571b8a922
Modify recognition that acquire_fence has been signaled
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: Id7d9ba288dae05b8c50ebb2090e3aa7ae8b61671
-40 to 125°C reliable, outside the range existed unreliability.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I7f24809bd7a4aa89a7fa12763081258468281fee
This patch set HS disconnect detect mode to single ended detect mode
for RV1106, fix RV1106 can not recognize device plug out sometimes.
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Change-Id: I6ee6ded4cc12032cf2825eadd207c1e5003957cd
Fixes: 5d33c809c3 ("ASoC: codecs: Add support for rockchip codec digital interface")
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I867538d4aef82120b9cefa2cf833ccfe43f11596
Workaround for FIFO clear on SLAVE mode:
A Suggest to do reset hclk domain and then do mclk
domain, especially for SLAVE mode without CLK in.
at last, recovery regmap config.
B Suggest to switch to MASTER, and then do FIFO clr,
at last, bring back to SLAVE.
Now we choose plan B here.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I1884659df7fa9052477652b7b0315da21e3165c2
The previous idea about FIFO clear on SLAVE mode is:
1, Switch to MASTER mode
2, Do FIFO clear
3, Switch to SLAVE mode
But, there is a risk that drivers don't set mclk on SLAVE mode,
the mclk from PLL maybe a very high freq (higher than controllers'
signoff freq) that make controller work unexpected.
This patch allow set mclk freq for MASTER / SLAVE mode to fix it.
and, of course, there is no side effect.
This patch also simplify the clear routine by merging clear step 1/2
into a single one.
Fixes: 0a0a0b7606 ("ASoC: rockchip: i2s-tdm: Fix FIFO clear error on SLAVE mode")
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I8488b039e1e21a632bfd2a1c48c86b343fded17a
The emmc power is turned off after it is suspended. The drivers
need to enable the power off notification, otherwise the emmc
initialization will take a long time during wake-up.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Iea233d378c0a7f313ebc39228b4e109cbb4a4f83
The emmc power is turned off after it is suspended. The drivers
need to enable the power off notification, otherwise the emmc
initialization will take a long time during wake-up.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I52ed6ecd3c5bb8eacf2b918a7b091e83db026594
The emmc power is turned off after it is suspended. The drivers
need to enable the power off notification, otherwise the emmc
initialization will take a long time during wake-up.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Ifbcfdc0b7821c85cc20d7a88c86c29b5343d7259
The emmc power is turned off after it is suspended. The drivers
need to enable the power off notification, otherwise the emmc
initialization will take a long time during wake-up.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I47d61aa0b3d310c3c5718e35dc4432111103ec19
As the clk_matrix_200m_src is critical clock.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I1efb315dd00de2aa4f4067a84f04f9370c91d915
This amends the following points:
- pull all RX messages from FIFO to TCPM while packet received and
GoodCRC sent.
- for TX success alert, just complete the tx status and GoodCRC will
be read out at RX process (GCRCSENT alert).
The above changes can fix the Source Caps packets may loss in PD
renegotiate stage probably.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I0422449842fd24e42e398a38446dc00477c7acce
Invoke set_pd_rx() may flush the RX FIFO of PD controller, so do
set_pd_rx() before sending Soft Reset in case Source caps may be flushed
at debounce time between SOFT_RESET_SEND and SNK_WAIT_CAPABILITIES state.
Without this patch, in PD charger stress test, the FUSB302 driver may
occur the following exceptions in power negotiation stage.
[ ...]
[ 4.512252] fusb302_irq_intn
[ 4.512260] AMS SOFT_RESET_AMS finished
[ 4.512269] state change SOFT_RESET_SEND ->SNK_WAIT_CAPABILITIES [rev3 NONE_AMS]
[ 4.514511] pd := on
[ 4.514516] pending state change SNK_WAIT_CAPABILITIES ->HARD_RESET_SEND @ 310 ms [rev3 NONE_AMS]
[ 4.515428] IRQ: 0x51, a: 0x00, b: 0x01, status0: 0x93
[ 4.515431] IRQ: BC_LVL, handler pending
[ 4.515435] IRQ: PD sent good CRC
[ 4.516434] PD message header: 0
[ 4.516437] PD message len: 0
[ 4.516444] PD RX, header: 0x0 [1]
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: Icf8748e319094bee5dd010e353254c532fdea6ab
The commit af02b05e59 ("mmc: add thunder boot support") reduced
the timeout time by mistake, which will cause mmc initialization error.
Fixes: af02b05e59 ("mmc: add thunder boot support")
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Ie84d20104d2ea389c2369d6d1985c6dae0de054f
