As npll rate may be changed according to vopl dclk rate on px30.
Change-Id: I4abc042b49ee06436ba5d69dc8adfa9460da37f7
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
NPLL should provide clock for vopl dclk on px30, and its rate will be
changed according to vopl dclk rate, so GPU can't use npll as parent
on px30.
Change-Id: Ib2c8c57020405bcd14070dcd7bc71cbfe18230e3
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
DPTPHYT22ULP is designed for chips that perform eDP/DP data
communication while operating at low power consumption.
The main link is a multi-gigabit transmitter macro which
enable speed up to 4.0Gbps data transmitter with optimized
power and die size, also it can be easily fabricated and
implemented in a video system. The AUX channel is a halfduplex,
bidirectional channel consisting of one differential pair,
supporting the bit rate of about 1Mbps.
Macro consists of multi-main link transmitter channels,
AUX channel, one PLL and bias-gen unit. The main link
transmitter performs dedicated P2S, clock generator,
driver with preemphasis and self-test. Each of the channels
can be turned off individually.
Change-Id: Idf58991ff1bdd4557c4cfadf2dc047e95eca7668
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
The Rockchip GPIO and pin control modules are only present on Rockchip
SoCs. Hence add a dependency on ARCH_ROCKCHIP, to prevent asking the
user about this driver when configuring a kernel without Rockchip
platform support.
Note that before, the PINCTRL_ROCKCHIP symbol was not visible, and
automatically selected when needed. By making it tristate and
user-selectable, it became visible for everyone.
Change-Id: Ibaa8fddc0f667711bd6fc82fe1865cf65720c1c3
Fixes: be786ac5a6 ("pinctrl: rockchip: make driver be tristate module")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20210316134059.2377081-1-geert+renesas@glider.be
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from commit febb4ee23a)
reason: In rk356x, due to the hardware, vepu and jpegd should
disable auto freqence.
Change-Id: I2da5b5a7fc3b86180aef28b378a7b651e31a6b7a
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
When using 24MHz reference clock, some devices can't identify
the SATA PM chip, And the signal quality is not as good as 100MHz.
so change the reference clock to 100MHz.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: If7d951a0b77d503f9faf1c1f88c78a9e07471e47
In order to silent the warning below:
mmc0: unspecified timeout for CMD6 - use generic
Fixes: 4734c45258 ("mmc: core: don't check card status when flushing cache")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I561fd8592c646a61d22b04e27a0fc0a6c9b01f4e
Both rk3568' spi is compatible with rk3036's spi design.
Change-Id: I952beb57c151e77165db781bc17ec782b6bc62a4
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
the sub_dev will be update by list_for_each_entry() and return !NULL
error pointer when no found subdev;
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I8d7db3b66c6c57b986a42cac9ed6eca53b72611e
https://android.googlesource.com/kernel/configs
commit 46f8bc810fbe ("Finalize min LTS version for S.")
android-base.config and android-base-conditional.xml:
-# CONFIG_RD_LZ4 is not set
+CONFIG_USERFAULTFD=y
+CONFIG_SHADOW_CALL_STACK=y
+CONFIG_XFRM_MIGRATE=y
+CONFIG_SONY_FF=y
+CONFIG_ANDROID_BINDERFS=y
+CONFIG_CRYPTO_CHACHA20POLY1305=y
+CONFIG_CRYPTO_XCBC=y
+CONFIG_KFENCE=y
from gki_defconfig:
+CONFIG_KFENCE_SAMPLE_INTERVAL=500
+CONFIG_KFENCE_NUM_OBJECTS=63
RD_LZ4:
Support future decompression of LZ4-compressed ramdisk images.
USERFAULTFD:
Patches for SELinux support and kernel page-fault restriction in
userfaultfd have been backported.
So from security perspective it should be safe to enable it in Android.
XFRM_MIGRATE:
To be able to update addresses of an IPsec SA, as required by
supporting MOBIKE
CHACHA20POLY1305 and XCBC:
To be able to use ChaCha20Poly1305 and AES-XCBC in IPsec
CONFIG_KFENCE_NUM_OBJECTS controls the constant memory overhead that
KFENCE introduces for its memory pool. By default it is 255 objects
(2Mb extra memory), but since concerns have been raised that low-memory
devices may not afford that, we are lowering the number of objects
to 63 (512Kb extra memory).
So far we haven't seen Android devices allocate more than 50 KFENCE
objects. Should the kernel exhaust the pool, KFENCE will stop allocating
new objects and fall back to SLAB/SLUB until one of the objects is
freed.
An immediate consequence of reducing the pool size is that a freed
KFENCE object will be reused 4x times faster, effectively reducing the
probability of detecting a use-after-free. Since KFENCE is a best-effort
error detection tool, not a use-after-free mitigation mechanism, we
believe this should not be problematic.
enable KFENCE by setting the sample interval to 500ms
It is still possible to disable KFENCE at boot time using
kfence.sample_interval=0.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I061f3caf0d09adfd4e0c322853aeff5af8ba63a5
According to commit f382fb0bce ("block: remove legacy IO schedulers").
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_CFQ_GROUP_IOSCHED=y
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ia20d8fe921b4ff0e4b8507ef665cae865704f717
A node is empty node if its proplist/label/child both null or both
set as deleted.
Change-Id: Ia934c58df3305dc9531cc912322eb2728f7af689
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Calculate current load with busytime / totaltime from status,
also show the current frequency.
Change-Id: Ic310035db9c5478aa3d0b1e526b47c451fe09d23
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
use rockchip_drm_sub_dev_list to manage rockchip drm sub dev and record
connector, offer new method to find connector through the sub_dev_list.
Change-Id: If9508cf9ff51f6f9e1d13c42c60491f4aec4b9c1
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
When get possible_crtcs for a encoder, skip the inactived endpoint, this
make userspace more clear about which crtc this connector should attached
to.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I4221491307193209482fd9477a492ebba613c7ad
We don't want to call rk_iommu_enable when iommu driver resume.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I5bd1ac97522af42b0e6178c28ed714c5f5d5206b
RK3568 has 3 pmu io-domain, pmuio0/1/2, but the pmuio0 is 1.8v only, and
pmuio1 is 3.3v only, only pmuio2 support to select 1.8v or 3.3v.
RK3568 also has 7 io-domain, vccio1/2/3/4/5/6/7, but the vccio2
defaultly selected by the FLASH_VOL_SEL(GPIO0_A7).
Change-Id: I55ea1263c641112705b1443ff919c508cb3be2f0
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
I think we want to fallback to non-iommu buffer if
iommu is disabled in dts.
Check for iommu->parent is meanless here.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I78ce028a9c1215f1e8f956916f775f07b30e67be
according to our testing results, added the ipa parameters for both cpu
big cores and cpu little cores, and updated the parameters for gpu.
for now,the gpu thermal zone is used only to get the gpu's temperature.
Change-Id: Ifc7708de9d880e0f9cd5da0bb71a135b0c381b45
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Fixes: 773a33a1cc ("drm/rockchip: gem: reorder pages if page chunk less than 8")
Change-Id: Ib3540e67d898d579179b86ec19e367d14478ac3d
Signed-off-by: Simon Xue <xxm@rock-chips.com>
The cpu_thermal node in the rk3399-rock960.dts file does not
reference &cpu_thermal directly to add the board-specific parts,
but also repeats all the SoC default properties.
Clean the whole thing up and fix alignment.
Place new nodes in the correct alphabetical order.
Compered to rk3399.dtsi the temperature property in
cpu_alert0 changes from <70000> to <65000>.
A sustainable-power property was added.
The trip property in cooling map0 points to <&cpu_alert1>
instead of <&cpu_alert0>.
Change-Id: Ic39c3c246446c87a933da382b2432670a830d095
Suggested-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20210118180054.9360-1-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from commit c73583c625)
A test with the command below gives for example this error:
/arch/arm64/boot/dts/rockchip/rk3399-evb.dt.yaml:
thermal-zones: 'cpu', 'gpu' do not match any of the regexes:
'^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$', 'pinctrl-[0-9]+'
Rename Rockchip rk3399 thermal subnodes so that it ends
with "-thermal"
make ARCH=arm64 dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/
thermal/thermal-zones.yaml
Change-Id: I10e9d6d8786557e50efb9a95ba701fe537d1884a
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20210117150953.16475-3-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from commit e58061b597)
Switch from rockchip defined PHY_MODE_VIDEO_xx
to stand PHY_MODE_xx
There is no PHY_MODE_TTL/RGB definition in stand
phy_mode, so use RGB as the default mode.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: Ie96c673c902881e651949cf63dce98c1005eb34c
Switch from rockchip defined PHY_MODE_VIDEO_xx
to stand PHY_MODE_xx
There is no PHY_MODE_TTL/RGB definition in stand
phy_mode, so use RGB as the default mode.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: Idaa632df3bf8cd31f1f1848e0b85444c56944fc8
Switch from rockchip defined PHY_MODE_VIDEO_xx
to stand PHY_MODE_xx
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: Id04fd6eba6438a41679044d1998cfb207aad02ca
Switch from rockchip defined PHY_MODE_VIDEO_xx
to stand PHY_MODE_xx
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I9421ea0b5d804671903a498e20b68b163d40e166
