The AP1511A is different from the BA6208.
ENB: low-active enable
FBC: Forward/Backward control
ENB FBC OUT1 OUT2
H X L L
L H H L
H L L H
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: Ieba00ed509b8d886dc22d8f0018a8282f3c73040
Fix warning:
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c:542: warning: Function
parameter or member 'phys_id' not described in
'vop2_find_win_by_phys_id'
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c:542: warning: Function
parameter or member 'vop2' not described in 'vop2_find_win_by_phys_id'
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c:3503
vop2_plane_create_name_property() warn: should '1 << (win->win_id)' be a
64 bit type?
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c:3509
vop2_plane_create_name_property() warn: should '1 << (win->win_id)' be a
64 bit type?
Fixes: efe0578ec8 ("drm/rockchip: Add support for vop2")
Change-Id: Ia52eac3fcf2ddeff825b5fdaa26adcf26c71a7af
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
The ISP and CMA need the operating system must not active the region.
Signed-off-by: Zhangbin Tong <zebulun.tong@rock-chips.com>
Change-Id: Id27f453f8f1734d992d0e5ae9c38a01b0f7686fe
Rockchip vop2 build on a unified architecture with
multi video output ports support.
For RK3568:
* 3 Video Port, every video port can drive a display timing independently.
* 6 graphic window: Cluster win x 2, Esmart win x 2, Smart wind x 2.
* 6 windows can be divided into 3 groups for independent overlay for
3 Video Ports.
* RGB/eDP/HDMI/MIPI get display timing from 1 of the 3 Video Ports.
+----------+ +-------------+
| Cluster | | Sel 1 from 6| +--------------------+
| window0 | | Layer0 | |n from 6| |
+----------+ +-------------+ | |Video Port0|
+----------+ +-------------+ |Overlay | |
| Cluster | | Sel 1 from 6| +--------+-----------+
| window1 | | Layer1 |
+----------+ +-------------+
+----------+ +-------------+
| Esmart | | Sel 1 from 6|
| window0 | | Layer2 | +--------------------+
+----------+ +-------------+ |n from 6| |
+----------+ +-------------+ | |Video Port1|
| Esmart | | Sel 1 from 6| |Overlay | |
| Window1 | | Layer3 | +--------+-----------+
+----------+ +-------------+
+----------+ +-------------+
| Smart | | Sel 1 from 6|
| Window0 | | Layer4 | +--------------------+
+----------+ +-------------+ |n from 6| |
+----------+ +-------------+ | |Video Port2|
| Smart | | Sel 1 from 6| |Overlay | |
| Window1 | | Layer5 | +--------+-----------+
+----------+ +-------------+
Change-Id: I4c42d655f75903066888b6aea92e926192b000c2
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Pixel blend modes represent the alpha blending equation
selection, describing how the pixels from the current
plane are composited with the background.
Adds a pixel_blend_mode to drm_plane_state and a
blend_mode_property to drm_plane, and related support
functions.
Defines three blend modes in drm_blend.h.
Changes since v1:
- Moves the blending equation into the DOC comment
- Refines the comments of drm_plane_create_blend_mode_property to not
enumerate the #defines, but instead the string values
- Uses fg.* instead of pixel.* and plane_alpha instead of plane.alpha
Changes since v2:
- Refines the comments of drm_plane_create_blend_mode_property:
1) Puts the descriptions (after the ":") on a new line
2) Adds explaining why @supported_modes need PREMUL as default
Changes since v3:
- Refines drm_plane_create_blend_mode_property(). drm_property_add_enum()
can calculate the index itself just fine, so no point in having the
caller pass it in.
- Since the current DRM assumption is that alpha is premultiplied
as default, define DRM_MODE_BLEND_PREMULTI as 0 will be better.
- Refines some comments.
Changes since v4:
- Adds comments in drm_blend.h.
- Removes setting default value in drm_plane_create_blend_mode_property()
as it is already in __drm_atomic_helper_plane_reset().
- Fixes to use state->pixel_blend_mode instead of using
plane->state->pixel_blend_mode in reset function.
- Rebases on drm-misc-next.
Change-Id: I021908dc42aef01e4b7c70f99904ccabffa4adfe
Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Lowry Li <lowry.li@arm.com>
Signed-off-by: Ayan Kumar Halder <ayan.halder@arm.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Link: https://patchwork.freedesktop.org/patch/245734/
(cherry picked from commit a5ec8332d4)
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
We can adjust the sensibility of the Aschip's PIR sensor via pulse gpio,
and the timing should be precise.
For example:
min: echo 4 > /proc/pir/sensibility
max: echo 100 > /proc/pir/sensibility
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: Id3e644fc38d9be24f97351df665e27fc4ff9d545
Switch is just a function of switching. There is no voltage setting
function. Voltage getting is the supply voltage.
Fixes: 3fc99e38fd ("regulator: resolve supply after creating regulator")
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Ia45677a24fbfb831226563c56bcb26885bb17db1
The key parameter (this_card) is invalid if the mmc_host drivers were
built as module.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: I250ce59591da542d7fc1e4afcd6d8442a82b1d17
Some i2s bus GPIOs maybe designed multiplex, the default
is input, we need to configure IN/OUT dynamically.
Change-Id: I2e0f0f972d6f9fa3fc8e8fc9f5dfd5d4e6deaee1
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
The function param_read() and param_exped() do the same thing,
so this patch uses the more general param_read() instead of
the param_exped(), and delete the param_exped() directly.
Change-Id: Ic097069c28a717ff5f70ceaa36a22ea1bd26b76f
Signed-off-by: William Wu <william.wu@rock-chips.com>
This reverts commit f86b9bf622 which is
commit f4ac712e4f upstream.
Jari Ruusu writes:
Above change "block: ratelimit handle_bad_sector() message"
upstream commit f4ac712e4f
in 4.19.154 kernel is not completely OK.
Removing casts from arguments 4 and 5 produces these compile warnings:
...
For 64 bit systems it is only compile time cosmetic warning. For 32 bit
system + CONFIG_LBDAF=n it introduces bugs: output formats are "%llu" and
passed parameters are 32 bits. That is not OK.
Upstream kernels have hardcoded 64 bit sector_t. In older stable trees
sector_t can be either 64 or 32 bit. In other words, backport of above patch
needs to keep those original casts.
And Tetsuo Handa writes:
Indeed, commit f4ac712e4f ("block: ratelimit handle_bad_sector() message")
depends on commit 72deb455b5 ("block: remove CONFIG_LBDAF") which was merged
into 5.2 kernel.
So let's revert it.
Change-Id: I5a83d4009db1aaed899b48724d757bb327b14a10
Reported-by: Jari Ruusu <jariruusu@users.sourceforge.net>
Reported-by: Tetsuo Handa <penguin-kernel@i-love.sakura.ne.jp>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Jens Axboe <axboe@kernel.dk>
Cc: Sasha Levin <sashal@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git
commit fd732693294f8d013ff14d5d1574acadb7fd9fc3)
This patch allows user to set MCLK_I2Sx_OUT2IO freq
by CLK_SET_RATE_PARENT.
Change-Id: Ie8f3163726d34c7cf3ee206bbc1d0866049d6eda
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
LDCH will compete with LSC/3DLUT for the DDR bus,
which may cause LDCH to read the map table exception.
so isp enable LDCH in 2th frame.
Signed-off-by: Xu Hongfei <xuhf@rock-chips.com>
Change-Id: If84139362ee9ca8de43714915f4387923cf21000
when iommu pagefault, mark_irq to disable iommu interrupt,
then handle the fault, and unmark_irq to enable hardware.
Change-Id: Id40868bfab67ac27e12c181d83a8e70a09a1e498
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
1. update safe read, limit max op size.
2. add dsp time init.
3. add dsp frame control msg.
4. support flip.
5. support file export/import, calib data read/write.
6. add align calculate func.
Signed-off-by: Zhenke Fan <fanzy.fan@rock-chips.com>
Change-Id: I714aec690d00c9aa6f7f4ef58c3616bfcbf238bb
This is useful for debuggers, and is already the default for clang
(incidentally). Make sure it is on for all users/compilers.
Bug: 160841764
Change-Id: Ibb9a0c6900728d4cce3eccb57fb4c38268a89f24
Signed-off-by: Alistair Delva <adelva@google.com>
