Fixes a build break when CONFIG_ROCKCHIP_PM_DOMAINS is not selected.
drivers/video/rockchip/mpp/mpp_common.c:2286:13: error: implicit declaration of function 'rockchip_pmu_pd_is_on' [-Werror,-Wimplicit-function-declaration]
pd_is_on = rockchip_pmu_pd_is_on(mpp->dev);
^
drivers/video/rockchip/mpp/mpp_common.c:2288:3: error: implicit declaration of function 'rockchip_pmu_pd_on' [-Werror,-Wimplicit-function-declaration]
rockchip_pmu_pd_on(mpp->dev);
^
drivers/video/rockchip/mpp/mpp_common.c:2304:3: error: implicit declaration of function 'rockchip_pmu_pd_off' [-Werror,-Wimplicit-function-declaration]
rockchip_pmu_pd_off(mpp->dev);
^
Fixes: 93993a9497 ("soc: rockchip: power-domain: export pd on/off and pd status")
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Idd4039639fb0884a6fccdec0e22f37888a301a98
hdmi->cec_adap may be null when system boot and hpd occur.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I208412b9b8b1e3fd846e62bf5e1f86e706d678e6
There is no need to call dw_hdmi_setup() when atomic_check.
dw_hdmi_color_changed() will check if color format changed and
call a mode_set.
If call dw_hdmi_setup() to enable hdmi when the first plug in
atomic_check, HPLL has not been configured in rk356x, there will
be display err in some monitor.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I83f3d1d3ff45e3e07910449d8d03f94b82fc0abe
Using get_output_bus_format() and get_input_bus_format() to get
bus format when dw-hdmi is only bridge.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Iec341cbb782270baafb8fa50752296d989def58b
hdr_static_metadata is no longer used for HDR configuration,
used only as store the hdr info after edid parsing.
Change-Id: Ib2c5e3e739267433176181aa9a0611a50a847125
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
For compatibility with GKI, HDR_PANEL_METADATA can't be a global
property. So change HDR_PANEL_METADATA to Rockchip private property.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I7926683a5dc6274e6cab2151e476344fa897b66c
* android12-5.10-2021-08: (429 commits)
ANDROID: Update symbol list for mtk
ANDROID: scheduler: export task_sched_runtime
FROMLIST: mm: slub: fix slub_debug disabling for list of slabs
FROMLIST: mm/madvise: add MADV_WILLNEED to process_madvise()
ANDROID: Update the exynos symbol list
FROMGIT: firmware: arm_scmi: Free mailbox channels if probe fails
ANDROID: GKI: gki_defconfig: Enable CONFIG_NFC
ANDROID: sched: Make uclamp changes depend on CAP_SYS_NICE
ANDROID: GKI: update xiaomi symbol list and ABI XML
ANDROID: ABI: update generic symbol list
ANDROID: scsi: ufs: Enable CONFIG_SCSI_UFS_HPB
ANDROID: scsi: ufs: Make CONFIG_SCSI_UFS_HPB compatible with the GKI
UPSTREAM: arm64: vdso: Avoid ISB after reading from cntvct_el0
ANDROID: GKI: Disable X86_MCE drivers
ANDROID: GKI: Update symbols to symbol list
ANDROID: ABI: update allowed list for exynos
FROMGIT: sched: Skip priority checks with SCHED_FLAG_KEEP_PARAMS
FROMGIT: sched: Don't report SCHED_FLAG_SUGOV in sched_getattr()
FROMGIT: sched/deadline: Fix reset_on_fork reporting of DL tasks
BACKPORT: FROMGIT: sched: Fix UCLAMP_FLAG_IDLE setting
...
Change-Id: I5e0600bb4ccd0333366b016b42332e1e79e56b61
Conflicts:
drivers/usb/gadget/configfs.c
include/linux/usb/gadget.h
RK1000 is a digital-analog mixed chip which has tve output function.
RK1000's registers can be written and read through I2C interaface.
Because RK1000's I2C need dclk and mclk, RK1000 TVE should be registered
after RK1000 CORE.
Change-Id: I65b40826bd1dbf07d4fa94ecdf8c75005008731f
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
RK1000's control register block need mclk for i2c communication.
So mclk should be enabled in advance.
RK1000's control register block should be registered before RK1000
TVE.
Change-Id: Iba9a2a410fe927666072f8d246995462a860ec3a
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
This driver is modified to support RK3588 SoCs.
Change-Id: I69aa0607ccac7256d40a5e6c89c8ba5d2155eb53
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
According to a description from TRM, add all the power domains.
Change-Id: I0ab9442b3310b04a8dc8e1a10c30d6754ca3e8f9
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
rk3588 is a full version chip and have more periphral interface base on
rk3588s.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I3280fcacb667f5ed49ca7146f26b7c256147d281
rk3588s is a small package version of rk3588, which have less
peripherial interface, so we use it as base version and rk3588 will be
the full version.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I56418768af54e76db3d751f3151ff056109b7f18
This initialize version support single core cpu, timer, uart and gic.
Add dmac device nodes.
Add cru device node.
Add sdhci node, rk3588 is using dwcmshc controller as eMMC controller.
The controller is different from that of rk3568 and the driver
needs to be identified and handled specially.
Add sdmmc0 node. Use temp xin24m clock, will need to update to smci clock
which is not ready for now.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I7fadb39ddb1827bdd5a816149f6e129b94ae2395
Add the clock tree definition for the new RK3588 SoC.
Change-Id: I055dafbe1587606c56a5553cbb3d4772bd84f97b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add the dt-bindings header for the rk3588, that gets shared between
the clock controller and the clock references in the dts.
Add softreset ID for rk3588.
Change-Id: I9fa9d27a187a6951c5c1cf210b0eff988a41457e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
In order to improve the main frequency of CPU, the clock path of CPU is
simplified as follows:
|--\
| \ |--\
--apll--|\ | \ | \
| |--apll_core--| \ | \
--24M---|/ |mux1 |--[gate]--|mux2|---clk_core
| / | /
--gpll--|\ | / |------| /
| |--gpll_core--| / | |--/
--24M---|/ |--/ |
|
-------apll_directly--------------|
When the CPU requests high frequency, we want to use MUX2 select the
"apll_directly".
At low frequencies use MUX1 to select “apll_core" and then MUX2 to
select "apll_core_gate".
However, in this way, the CPU frequency conversion needs to be
in the following order:
1. MUX2 select to "apll_core_gate", MUX1 select "gpll_core"
2. Apll sets slow_mode, sets APLL parameters, locks APLL, and then APLL
sets normal_mode
3. MUX1 select "apll_core", MUX2 select "apll_directly"
So add pre_muxs and post_muxs to cover this special requirements.
Change-Id: I944c22f774f5f9c4edaf28099b6c2926076d4749
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
add pll_rk3588 and pll_rk3588_core type for RK3588 Soc.
Change-Id: Ie84adcb1ff8fe59efc212feee3ed872bb318fc8b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Document the device tree bindings of the rockchip Rk3588 SoC
clock driver in
Documentation/devicetree/bindings/clock/rockchip,rk3588-cru.yaml.
Change-Id: Ic5b5bbb017c477658d3ae0119c8ec22685daa837
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The cores select parent register is special on RK3588.
Change-Id: I1cfd07064ae7092030a6b9d234049e6cf07a23e8
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Refactor conversion operation to support new saradc, separate
start, read, powerdown in respective hooks.
Change-Id: Iacb043d14f7867b45bf0c4c74c2bedd21d398944
Signed-off-by: Simon Xue <xxm@rock-chips.com>
