set pll sequence:
->set pll to slow mode or other plls
->set pll down
->set pll params
->set pll up
->wait pll lock status
->set pll to normal mode
To slove the system error:
rockchip_rk3399_wait_pll_lock: timeout waiting for pll to lock
rockchip_rk3399_pll_set_params: pll update unsucessful,
trying to restore old params
Change-Id: I62aecd9f292de5a3c7bcd8a87231785bf115159d
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
If setting freq is not support in rockchip_pll_rate_table rk3399_pll_rates[],
It can set pll params by auto.
Change-Id: I5016cece64dca4c2efec18d552ee6be426f6b95a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add cru regs dump when system panic.
It's just for debug.
Change-Id: I3aeeeb7f7b9240c917c18bc2d36b082003dc6370
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Rockchip socs often have some tiny number of muxes not controlled from
the core clock controller but through bits set in the pmugrf.
Use MUXPMUGRF() to cover this special clock-type.
Change-Id: Iac962a27a3c88ce188d03c416cb4b3b45a462c0a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
There is a new clock branch have a form like
|--\
Change-Id: I6a7c17cb782b13965f537f44c103611e00d1ecad
---[GPLL]---| \ |--\
---[CPLL]---|mux|-----[GATE]--[DVI]------| \
---[HPLL]---| / | |mux|--[GATE]--
|--/ |--[GATE]--[HALFDVI]--| /
|--/
This patch registers two composite clocks for this branch type,
and make them become brother clock for each oher.
Change-Id: I46aeab26e478f341600114014db1c7d58e234f11
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Some composite clocks may have the same parent clock, if one clock change
the parent clock rate, the other clock rate may too large, so add a
brother clock in composite that the other clock also can be changed when
parent rate is changed.
Change-Id: I2c6749e578b76d6780cecdcd9ff1b5fd4f25a0ba
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The CLK_SET_RATE_PARENT flag make the parent clock and the child clk is 1:1.
If the DCLK frequency is too low, the PLL frequency will be very
low, which will affect the output waveform quality of PLL, and PLL
locking may be abnormal, so add a new COMPOSITE_DCLK clock-type to handle
that.
Change-Id: If9bee9ebf157fcf034aed246b3aa1cff503ef9cf
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
We know that under the condition of even frequency division,
if the numeratoris greater than 4, the duty cycle may not be
equal to 50%.
In the case, weneed to keep the original numerator(<4) and
denominator.
Change-Id: I8cd08199df4e3d27d5697ce80370224a6f267e26
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
From Rockchips fractional divider usage, some clocks can be generated
by fractional divider, but the input clock frequency of fractional
divider should be less than a specified value.
Change-Id: Ifd6c5f6a24a64021f990506e8657cd925f9b96f9
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The bigger the divider, the better the clock jitter.
Change-Id: I4b4e06c71c2f0bdb0e32422fb42c8d490c3ec4bd
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The div offset of some clocks are different from their mux offset
and the COMPOSITE clock-type require that div and mux offset are
the same, so add a new COMPOSITE_DIV_OFFSET clock-type to handle
that.
Change-Id: I1c97f7464c3c80ea6dbd7d4052565dd4e35c0931
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
A clock branch consisting of a mux with non-standard
select values.
The parent in Mux table is sorted by priority.
Change-Id: Ibcaa35541cf8bc255175a62c7950b2241aac2f55
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
With features AVB / dm-verity enabled, cmdline content is about to
exceed previous maximum 2048 bytes. printk can not support long line
exceed LOG_LINE_MAX which less than 1024. So loop printk until all
content are printed in init/main.c.
Change-Id: I4c40b5302d82122b93161fe30082f5abcfcad069
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
dtc generation of symbols by CONFIG_DTC_SYMBOLS.
For support device tree overlay.
Change-Id: Ia10496031bc02fd3a4ff98ab0acfc6fc9a54951b
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
-CONFIG_MEMCG_SWAP=y which default y
-CONFIG_SECCOMP=y which default y
-CONFIG_POWER_AVS=y which is removed upstream.
-CONFIG_ZBOOT_ROM_TEXT=0x0 which default 0x0
-CONFIG_ZBOOT_ROM_BSS=0x0 which default 0x0
reorder some configs.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ifc45b074751a9ef8d0e5390102fe6c4cc9d5bab2
-CONFIG_MEMCG_SWAP=y which default y
-CONFIG_SECCOMP=y which default y
-CONFIG_POWER_AVS=y which is removed upstream.
reorder some configs.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I1b5651ce91a06f69a6cafb116ad2b67c1850a0a1
This reverts part of commit 251c226c35 ("rk: revert to v4.19").
To keep the changes of include/dt-bindings/soc/rockchip,boot-mode.h.
Change-Id: I4bcb721da1bea0600c92d4e23d33320bff8d0caf
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
There is not need to build mach-rockchip when PSCI is enabled.
Save about 5K text, 7K data and fix compilation error for THUMB2_KERNEL.
Change-Id: Ieb17867592d7d49a8b983dc5c7e8d1d1df14d864
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
The lz4 Legacy format(which specified by -l) is
not supported by U-Boot.
Change-Id: I6b94881117b59384daca4efd796c933e8dc9e5a6
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
fs/incfs/format.c: In function 'incfs_read_next_metadata_record':
./include/linux/kern_levels.h:5:18: warning: format '%ld' expects argument of type 'long int', but argument 2 has type 'size_t {aka unsigned int}' [-Wformat=]
fs/incfs/format.c:619:3: note: in expansion of macro 'pr_warn'
pr_warn("incfs: The record is too large. Size: %ld",
^~~~~~~
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I1a0b1e32761dd4358ff3ca210041893373f0a1a5
Test on RV1126 board with UVC function. When do UVC streaming on/off
@H265 3840 * 2160 stress test, it fails to streaming on UVC with the
following log:
[ 1589.834573] WARNING: CPU: 3 PID: 3075 at drivers/usb/dwc3/gadget.c:1611 dwc3_gadget_ep_queue+0x148/0x178
[ 1589.834593] ep3in: request 638c13d3 already in flight
[ 1589.834603] Modules linked in: galcore(O)
[ 1589.834622] CPU: 3 PID: 3075 Comm: kworker/3:2 Tainted: G W O 4.19.111 #2
[ 1589.834631] Hardware name: Generic DT based system
[ 1589.834648] Workqueue: events uvcg_video_pump
[ 1589.834673] [<b010f408>] (unwind_backtrace) from [<b010b96c>] (show_stack+0x10/0x14)
[ 1589.834741] [<b010b96c>] (show_stack) from [<b0645104>] (dump_stack+0x90/0xa4)
[ 1589.834766] [<b0645104>] (dump_stack) from [<b0126204>] (__warn+0xfc/0x114)
[ 1589.834787] [<b0126204>] (__warn) from [<b0126260>] (warn_slowpath_fmt+0x44/0x68)
[ 1589.834806] [<b0126260>] (warn_slowpath_fmt) from [<b04571d8>] (dwc3_gadget_ep_queue+0x148/0x178)
[ 1589.834826] [<b04571d8>] (dwc3_gadget_ep_queue) from [<b0472074>] (uvcg_video_pump+0x94/0x164)
[ 1589.834849] [<b0472074>] (uvcg_video_pump) from [<b013cce0>] (process_one_work+0x1f0/0x408)
[ 1589.834869] [<b013cce0>] (process_one_work) from [<b013d9b8>] (worker_thread+0x30/0x564)
[ 1589.834891] [<b013d9b8>] (worker_thread) from [<b0142910>] (kthread+0x140/0x170)
[ 1589.834907] [<b0142910>] (kthread) from [<b01010d8>] (ret_from_fork+0x14/0x3c)
[ 1589.834922] Exception stack(0xbbdfffb0 to 0xbbdffff8)
[ 1589.834938] ffa0: 00000000 00000000 00000000 00000000
[ 1589.834953] ffc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 1589.834966] ffe0: 00000000 00000000 00000000 00000000 00000013 00000000
[ 1589.834979] ---[ end trace b30d445a1f050523 ]---
[ 1589.834979] ---[ end trace b30d445a1f050523 ]---
[ 1589.834992] Failed to queue request (-22).
It's because that the __dwc3_gadget_start_isoc is called very late after
XferNotReady, so the frame number is outdated and start transfer fail
with the cmd_status "DEPEVT_TRANSFER_BUS_EXPIRY". In this case, the dwc3
driver return -EINVAL to the UVC function driver without delete and unmap
the failed request, this cause the request requeue fail next time.
Change-Id: I4cc919bcd4e1e0abbb6a929483e6fc2fe7dc9750
Signed-off-by: William Wu <william.wu@rock-chips.com>
Currently __dwc3_gadget_start_isoc must be called very shortly after
XferNotReady. Otherwise the frame number is outdated and start transfer
will fail, even with several retries.
DSTS provides the lower 14 bit of the frame number. Use it in combination
with the frame number provided by XferNotReady to guess the current frame
number. This will succeed unless more than one 14 rollover has happened
since XferNotReady.
Start transfer might still fail if the frame number is increased
immediately after DSTS is read. So retries are still needed.
Don't drop the current request if this happens. This way it is not lost and
can be used immediately to try again with the next frame number.
With this change, __dwc3_gadget_start_isoc is still not successfully in all
cases bit it increases the acceptable delay after XferNotReady
significantly.
Change-Id: I656b487b9a265921ae612a071ebcd496ffe5f510
Reviewed-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Michael Olbrich <m.olbrich@pengutronix.de>
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Felipe Balbi <balbi@kernel.org>
Signed-off-by: William Wu <william.wu@rock-chips.com>
(cherry picked from commit c5a7092f40)
It was recommended by ECN document, so following it will make
less risk in probing devices in case the refclk is coming from
SoC.
Change-Id: Ic4514f373b6014c406d5436738419c64df6d32b2
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
To support multi-display output_if must be clean when
hdmi disable.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ic4205a59ce1adab7f4ac6f673c740a14556fdeae
