As the HDMI-audio/codec will cause the hang on bootup, the root
cause that kylin get the invalid master clock from i2s.
$cat/sys/kernel/debug/clk/clk_summary
..
i2s_pre 0 0 0 0 0
sclk_i2s 0 0 0 0 0
i2s_clkout 0 0 0 0 0
Since i2s clock selects io input clock by default, but the hardware
didn't supply the clock.
This patch will fix the sclk_i2s's parent on i2s_frac.
As following:
$cat/sys/kernel/debug/clk/clk_summary
..
i2s_src 1 1 594000000 0 0
i2s_frac 1 1 22579200 0 0
i2s_pre 2 2 22579200 0 0
sclk_i2s 1 1 22579200 0 0
As far, the audio can work with aplay/record on kylin.dts
Says:
(aplay /dev/urandom)
/* recording */
arecord -f cd -d 10 /tmp/audio.wav
/* playback */
aplay /tmp/audio.wav
Change-Id: I73534a0d763eb02fb55e000ce068d9d604bf20ed
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
As the cpu frequency is less than 816MHz, the HDMI display maybe
probably cause a flower screen as below log[0]. And Kylin used the rk3036g
series SoCs that the max cpu frequency supported the 1GHz, not 1.2GHz.
In a word, keep the cpu frequency to 1GHz for kylin board.
log[0]:
[26.498843] rk_iommu 10118300.iommu: Enable stall request timed out,
status: 0x000011
[26.528809] rk_iommu 10118300.iommu: Disable paging request timed out,
status: 0x000011
[26.598849] rk_iommu 10118300.iommu: Enable stall request timed out,
status: 0x000011
[26.607579] rockchip-vop 10118000.vop: Failed to attach iommu device
[26.614916] rockchip-vop 10118000.vop: failed to attach dma mapping, -110
..
Change-Id: I8e1d4527b649d8857a9d80a121c10935a4cd1030
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
As the emmc is supplyed power by vcc_io, that's 3.3v voltage.
the default 1.8v volatge will cause the emmc error. as the following:
[ 17.096082 ] mmcblk1: error -115 sending stop command, original cmd
response 0x900, card status 0xb00
[ 17.127022 ] mmcblk1: error -110 transferring data, sector 664720, nr
72, cmd response 0x900, card status 0xb00
Remove the mmc-ddr-1_8v to keep the default the 3.3v voltage.
Change-Id: I9e2539d63fd93e72d9febbb311fbd686c5a11d09
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This patch supported the gpu opp table for rk3036.
The gpu clock's parent is DPLL, the default frequency is 400MHz, we need
assign 400MHz for gpu to be better working.
There is a quickly way for testing the gpu scaling frequency.
As following:
"
unset FREQS
read -a FREQS < /sys/class/devfreq/10091000.gpu/available_frequencies
RANDOM=$$$(date +%s)
while true; do
echo userspace > /sys/class/devfreq/10091000.gpu/governor
FREQ=${FREQS[$RANDOM % ${#FREQS[@]} ]}
echo GPU:Now ${FREQ}
echo ${FREQ} > /sys/class/devfreq/10091000.gpu/userspace/set_freq
sleep 1
done
"
Change-Id: Ia8eb3074e457014c497338a0a129551c51450104
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This patch supported the cpu voltage by changed with different
frequency, otherwise we will hit the following error on bootup.
..
[ 5.031516] cpu cpu0: Failed to get cpu_reg
[ 5.047725] cpu cpu0: clk or regulater is unavailable
..
Also, remove the 408M and 600M for rk3036 board, as the pclk_hdmi's parent
on apll, the low frequency will make the pclk be bad for hdmi display.
Change-Id: Ia4aac76a08cad3a59c33cd81065f943201a23a35
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This patch fixes the BT power reported the failure message.
As following:
root@linaro-alip:~# echo 1 > /sys/class/rfkill/rfkill0/state
[ 892.558269] rockchip-pinctrl pinctrl: pin gpio0-19 already requested
by 20060000.serial; cannot claim for wireless-bluetooth
[ 892.571052] rockchip-pinctrl pinctrl: pin-19 (wireless-bluetooth) status -22
...
And for now, the BT can work with this patch.
root@linaro-alip:~# echo 1 > /sys/class/rfkill/rfkill0/state
[ 69.328768] [BT_RFKILL]: ENABLE UART_RTS
[ 69.438540] [BT_RFKILL]: DISABLE UART_RTS
[ 69.443117] [BT_RFKILL]: bt turn on power
...
root@linaro-alip:~# hcitool dev
Devices:
hci0 94:A1:A2:E9:2D:18
And
root@linaro-alip:~# bluetoothctl
[NEW] Controller 94:A1:A2:E9:2D:18 linaro-alip [default]
[bluetooth]# scan on
Discovery started
[CHG] Controller 94:A1:A2:E9:2D:18 Discovering: yes
..
Change-Id: I2148f4203300ab4265fd3ba718f0d3ec0c57e7ca
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
It allows me to set the mac address in the bootloader.
Change-Id: Iad988205c6953e843e62aec67daad52128086324
Signed-off-by: Randy Li <randy.li@rock-chips.com>
There is a combo of a HEVC decoder and a VPU1 decoder at rk3036.
Change-Id: Ia7174cc9e2f2d640a74271077bd62cc68f3482b4
Signed-off-by: Randy Li <randy.li@rock-chips.com>
In order to save power and improve the performance, we can add the opp
table for rk3036 SoCs.
Also, make sure the codec works happily, we should ensure the arm/logic
voltage is greater than 1v.
Change-Id: I9aa17be547eb21e5a83c09780356436c3075bae6
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
In order to support the ap6212 module with rockchip wlan driver,
the kylin dts has to change the below for working.
1) We should add the 'supports-sdio' property for mmc tuning,
that's the rockchip private property, not on the upstream.
2) We should add the wifi power control pin and wifi/bt data for dts,
Maybe the history issue, they like the old driver for power
contronlling, the upstream didn't need these for working. we should
remove it in the future.
Change-Id: Id49de7ad77b8658a551a07659a8a2ddc9691874c
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
As the inno-hdmi driver introduced this clock, add it for dts supporting.
Change-Id: I43328a25f0ac72d5a5b7631cc8ff6ce98b78669a
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
In rk3036, the voltages of CPU and GPU are controlled by the same
regulator 'vdd_cpu'.
Here, we fix it to 1.25v to ensure that GPU could work well in
development period.
The actual voltage GPU needs might be much lower, and relative to
the frequence GPU runs at. this would be optimized when we implement
GPU DVFS with devfreq.
Change-Id: Ia25f0a67577fbfe248a25e4d913dc5f14fa40f0d
Signed-off-by: chenzhen <chenzhen@rock-chips.com>
I don't need send for upstream since the rockchip inside kernel
need it for tuning. At least the upstream can work it with dwmmc.
Change-Id: Ia9f0836624e8ef1df225dbc6ad1792ec4fb2abbd
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
On some xHCI controllers (e.g. Rockchip RK3399/RK3328/RK1808),
which are integrated in DWC3 IP, need to enable the Evaluate
Next TRB(ENT) flag in the TRB data structure to force xHC to
pre-fetch the next TRB of a TD. It's useful for the stability
of xHCI when transfer large data.
I have verify this patch on the following three cases:
Case 1:
On RK3399/RK3399Pro platforms, I found that when USB 3.0
read/write at the same time in the following test case,
it may easily fail without this patch.
Host transfer: 1024B, 4MB, 4MB, 4MB
Device transfer: 1024B, 4MB, 4MB, 4MB
Both Host and Device transfer "24B, 4MB, 4MB, 4M" Repeatedly
until transfer fail.
Case 2:
On RK3399 platform, Type-C1 USB 3.0 port connects with HUB
and Orbbec USB 3.0 Camera with the enumeration information:
usb 5-1: new high-speed USB device number 2 using xhci-hcd
usb 5-1: New USB device found, idVendor=05e3, idProduct=0610
usb 5-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
usb 5-1: Product: USB2.1 Hub
usb 5-1: Manufacturer: GenesysLogic
hub 5-1:1.0: USB hub found
hub 5-1:1.0: 2 ports detected
usb 6-1: new SuperSpeed USB device number 2 using xhci-hcd
usb 6-1: New USB device found, idVendor=05e3, idProduct=0620
usb 6-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
usb 6-1: Product: USB3.1 Hub
usb 6-1: Manufacturer: GenesysLogic
hub 6-1:1.0: USB hub found
hub 6-1:1.0: 2 ports detected
usb 5-1.2: new high-speed USB device number 3 using xhci-hcd
usb 5-1.2: New USB device found, idVendor=2bc5, idProduct=050d
usb 5-1.2: New USB device strings: Mfr=2, Product=1, SerialNumber=3
usb 5-1.2: Product: USB
usb 5-1.2: Manufacturer: USB
usb 5-1.2: SerialNumber: USB
uvcvideo: Found UVC 1.00 device USB (2bc5:050d)
usb 6-1.2: new SuperSpeed USB device number 3 using xhci-hcd
usb 6-1.2: New USB device found, idVendor=2bc5, idProduct=060d
usb 6-1.2: New USB device strings: Mfr=1, Product=2, SerialNumber=0
usb 6-1.2: Product: Orbbec(R) Astra(TM)
usb 6-1.2: Manufacturer: Orbbec(R)
Without this patch, it's possible to fail to open the Orbbec USB 3.0
camera or fail to preview image.
Case3:
On RK3399Pro platform, transfer the NPU data between the NPU USB 3.0
device and RK3399 USB 3.0 host.
Change-Id: I87b1d8b8b6912d77b988362f2f6dcd7766da8b0e
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch add a new property "snps,xhci-trb-ent-quirk" for
xHCI integrated in DWC3 IP to enable the Evaluate Next TRB(ENT)
flag in the TRB data structure.
Change-Id: I40b015b75f91c31d43f8f9ec1c80140f6140f86c
Signed-off-by: William Wu <william.wu@rock-chips.com>
On some xHCI controllers (e.g. Rockchip RK3399/RK3328/RK1808),
they need to enable the ENT flag in the TRB data structure to
force xHC to pre-fetch the next TRB of a TD. This patch add
a new quirk to enable the ENT flag.
And this patch also avoids to enable the ENT flag in the
following two cases:
1. The transfer length of the first TRB isn't an integer
multiple of the EP maxpacket.
2. The EP support bulk streaming protocol.
Change-Id: Ib7cc095a848f0846ad995529ad703ae4e4ee4d44
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch adds a new "xhci-trb-ent-quirk" property for some
Rockchip platforms which need to enable the ENT flag in the
TRB to force the xHC to pre-fetch the next TRB of a TD.
Change-Id: I670cfc759433b858feb1d5bb2805c793b050328a
Signed-off-by: William Wu <william.wu@rock-chips.com>
According to the "6.4 Transfer Request Block (TRB)" in xHCI
Specification, the max transfer length of a TRB is 64KB.
However, on Rockchip platforms which support xHCI in DWC3 IP
have problem if transfer more then 4KB in one TRB.
We don't know the root cause, maybe it's the DWC3 Tx/Rx FIFO
related, such as RK3399, it only support Tx FIFO 4136 Bytes
and Rx FIFO 3072 Bytes for SS Bus instance.
With the patch, it can make the xHCI transfer more stable on
Rockchip platforms, but it also cause transfer performance
loss. I test on RK3399 EVB Type-C USB 3.0 port with UAS USB 3.0
SSD, it cause 10% performance loss when use dd command to read/
write the UAS USB 3.0 SSD (350MBps -> 315MBps).
Change-Id: I11b10f6618d54d4cb0a778e5c0b4216227184e47
Signed-off-by: William Wu <william.wu@rock-chips.com>
The DWC3 with Innosilicon USB 3.0 PHY on Rockchip platforms
(e.g. rk3328, rk1808) has problem to exit to U0 state from
U1 or U2 state when DWC3 work as peripheral mode. This patch
adds a quirk to reject transition to U1 and U2 state to
workaround this issue.
Change-Id: Ib5a7a603193df23e4d274681bad155d005238349
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch adds a quirk for some special platforms (e.g.
rk1808 platform) which has problem to exit to U0 state
from U1 or U2 state when dwc3 work as peripheral mode.
To workaround this issue, we can add this quirk to reject
transition to U1 and U2 state.
Change-Id: I611b3562800e77079193cd5e96f6fe30bb3ca88a
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch fix the following build error if CONFIG_USB
is disabled and only support dwc3 gadget mode:
dwc3-rockchip.c:894: undefined reference to `usb_add_hcd'
dwc3-rockchip.c:622: undefined reference to `usb_remove_hcd'
......
dwc3-rockchip-inno.c:268: undefined reference to `usb_remove_hcd'
dwc3-rockchip-inno.c:286: undefined reference to `usb_add_hcd'
Change-Id: Iaa51ccc642abf5741fcd0d918967954c840240d5
Signed-off-by: William Wu <william.wu@rock-chips.com>
Support rockchip,rk1808-dwc3 for rk1808 board.
Change-Id: I68d9233e8cdf4704b54eb1fe2f17baf43ab6caf5
Signed-off-by: William Wu <william.wu@rock-chips.com>
Add a new property "xhci-slow-suspend" for some xHCI controllers
(e.g. Rockchip SoCs) which are integrated in DWC3 IP, they need
an extraordinary delay to wait for xHCI enter the Halted state
(i.e. HCH in the USBSTS register is '1'), especially if DWC3 is
in DRD mode.
Change-Id: Iffda2125ce403dd2ea9ca47b779580bdc3303b41
Signed-off-by: William Wu <william.wu@rock-chips.com>
If an xhci platform needs an extraordinary delay to wait for
xHCI enter the Halted state after the Run/Stop (R/S) bit is
cleared to '0', then add a property "xhci-slow-suspend" in
its pdev (like dwc3 host.c) to enable XHCI_SLOW_SUSPEND quirk.
Change-Id: If37fe7b7b37cc3c573361f4ef522404ebe39991e
Signed-off-by: William Wu <william.wu@rock-chips.com>
On some xHCI controllers (e.g. Rockchip SoCs), which are
integrated in DWC3 IP, need an extraordinary delay to wait
for xHCI enter the Halted state(i.e. HCH in the USBSTS
register is '1'), especially if DWC3 is in DRD mode.
Change-Id: I67c84d4768df95f7616d6716a77cf743e4334122
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Add rockchip specific glue layer to support USB3 Peripheral mode
and Host mode on rockchip platforms (e.g. rk3399).
The DesignWare USB3 integrated in rockchip SoCs is a configurable
IP Core which can be instantiated as Dual-Role Device (DRD), Host
Only (XHCI) and Peripheral Only configurations.
We use extcon notifier to manage usb cable detection and mode switch.
Enable DWC3 PM runtime auto suspend to allow core enter runtime_suspend
if USB cable is dettached. For host mode, it requires to keep whole
DWC3 controller in reset state to hold pipe power state in P2 before
initializing PHY. And it need to reconfigure USB PHY interface of DWC3
core after deassert DWC3 controller reset.
The current driver supports Host only and Peripheral Only well, for
now, we will add support for OTG after we have it all stabilized.
Change-Id: I821dd19eedec73e6517f0cca184f939a9f313904
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch fixes somme compile errors base on new extcon
API and new xHCI port structure.
Change-Id: I079815c283d5f047ab755cc8e3aa148919817b84
Signed-off-by: William Wu <william.wu@rock-chips.com>
The DWC3 rockchip driver provides a sysfs interface "dwc3_mode"
to force Peripheral mode or Host mode. It has a problem to force
to Host mode when the DWC3 works as Peripheral mode and connects
to Host (e.g. PC USB Port).
This issue can be reproduced on RK1808 EVB follow these steps:
1. Set dr_mode = "otg" in DTS dwc3 node;
2. Start the system, and connect the RK1808 USB 3.0 to PC USB.
3. Make sure that PC has recognized the USB device, and then
force DWC3 to Host mode via "dwc3_mode".
echo "host" > /sys/devices/platform/usb/dwc3_mode
And plug in an USB 2.0 Device to RK1808 USB 3.0 Port, then
we can see the following error log:
rockchip-dwc3 usb: Peripheral disconnect timeout
rockchip-dwc3 usb: USB unconnectedxhci-hcd
xhci-hcd.3.auto: xHCI Host Controller
xhci-hcd xhci-hcd.3.auto: new USB bus registered, assigned bus number 3
xhci-hcd xhci-hcd.3.auto: hcc params 0x0220fe64 hci version 0x110 quirks 0x04010010
...
hub 4-0:1.0: USB hub found
hub 4-0:1.0: 1 port detected
rockchip-dwc3 usb: USB HOST connected
rockchip-dwc3 usb: set new mode successfully
usb 3-1: new high-speed USB device number 2 using xhci-hcd
usb 3-1: new high-speed USB device number 3 using xhci-hcd
usb usb3-port1: attempt power cycle
usb 3-1: new full-speed USB device number 4 using xhci-hcd
usb 3-1: Device not responding to setup address
usb 3-1: Device not responding to setup address
usb 3-1: device not accepting address 4, error -71
It's because that in this test case, the dr_mode is original otg
mode, and the current code only call phy_set_mode() to disconnect
the peripheral from PC host if the dr_mode is peripheral mode.
This cause dwc3_rockchip_otg_extcon_evt_work() wait peripheral
disconnect timeout, and DWC3 fail to do runtime suspend and resume
to initialized the DWC3 core register again.
This patch call phy_set_mode() to disconnect the peripheral if
the current dr_mode is peripheral or otg when force to host mode.
Change-Id: I733d364046abcb616cf3d99ed57ab8604a87eef6
Signed-off-by: William Wu <william.wu@rock-chips.com>
In dwc3_rockchip_async_probe(), if it tries to get hcd in
peripheral only mode (dr_mode = "peripheral"), a NULL pointer
deference will happen. Because hcd only be allocated and
initialized in host mode or otg mode.
We can reproduce this issue when set dr_mode to peripheral
in DTS, like rk3399pro-npu.dtsi, and get the following panic
log on RK1808 EVB:
Unable to handle kernel NULL pointer dereference at virtual address 000000b0
pgd = ffffff8008b0b000
[000000b0] *pgd=000000007fffe003, *pud=000000007fffe003, *pmd=0000000000000000
Internal error: Oops: 96000005 [#1] PREEMPT SMP
Modules linked in:
CPU: 0 PID: 29 Comm: kworker/u4:1 Not tainted 4.4.167 #493
Hardware name: Rockchip RK1808 EVB V10 Board (DT)
Workqueue: events_unbound async_run_entry_fn
task: ffffffc07cd29580 task.stack: ffffffc07cd40000
PC is at dwc3_rockchip_async_probe+0x28/0x1c8
LR is at async_run_entry_fn+0x48/0x100
pc : [<ffffff80083adf5c>] lr : [<ffffff80080b445c>] pstate: 60000045
sp : ffffffc07cd43d10
...
[<ffffff80083adf5c>] dwc3_rockchip_async_probe+0x28/0x1c8
[<ffffff80080b445c>] async_run_entry_fn+0x48/0x100
[<ffffff80080acca8>] process_one_work+0x1b8/0x2b8
[<ffffff80080ad94c>] worker_thread+0x304/0x418
[<ffffff80080b206c>] kthread+0xd0/0xd8
[<ffffff8008082e80>] ret_from_fork+0x10/0x50
Fixes: f2a2b34e45 ("usb: dwc3: rockchip: use async_schedule for initial dwc3")
Change-Id: I740936e43bc4ea2b5a056d6d9dcaf18466006f0c
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch uses the devm_extcon_register_notifier to
manage the resource automatically.
Change-Id: I427c54d59283ee97623ad829e42dac40516c3df4
Signed-off-by: William Wu <william.wu@rock-chips.com>
RK3399 Excavator Board has an USB 3.0 PHY power on issue
when Type-A USB 3.0 Host port connects with an USB 3.0
device and do system PM suspend/resume test.
When the issue happens, we gets the following error log:
phy phy-ff800000.phy.4: phy poweron failed --> -110
dpm_run_callback(): platform_pm_resume+0x0/0x54 returns -110
PM: Device fe900000.dwc3 failed to resume: error -110
xhci-hcd xhci-hcd.12.auto: port 0 resume PLC timeout
It's because that the Type-C PHY docs say that the DWC3
controller "needs to be held in reset to set the PIPE
power state in P2 before initializing the Type-C PHY",
but actually the PIPE is in P0 state because an USB 3.0
device is connected, and the current code doesn't reset
the DWC3 controller upon PM resume.
This patch prevents powering off the USB 3.0 PHY of
RK3399 Type-A USB 3.0 Host port when system enters
syspend. As a side effect, the power consumption in
standby mode will increase. However, if you want to
optimize the power consumption in standby mode and
allow the USB device to be reenumerated upon PM resume,
you can add a property "needs-reset-on-resume" in
DWC3 DTS like this:
&usbdrd3_1 {
needs-reset-on-resume;
};
Change-Id: Ia1cdf6e09cac520e99931a15423b8de7be2ba52b
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch assigns the pd_usb3 power domain to the parent of
dwc3 node.
Change-Id: I2074539c23f958041d8829f7b3826a7813c3631a
Signed-off-by: William Wu <william.wu@rock-chips.com>
Adds pm_runtime support for some rockchip SoCs (e.g. rk3399)
which support power domain for USB 2.0 PHY.
Change-Id: I4c78075c884b3baf6d709e08e3464b214524d685
Signed-off-by: William Wu <william.wu@rock-chips.com>
Assign the pd_perihp power-domain to the USB 2.0 PHY node.
Change-Id: I9fda0a4391a6fb3823293b3dd36cae7cd6da0fb5
Signed-off-by: William Wu <william.wu@rock-chips.com>
Instead of indirectly selecting EXTCON via depending on
EXTCON, just select EXTCON. It is possible to avoid modify
lots of defconfig.
Change-Id: Id4a633404d543b87dda86b126fd6aab1d53c1415
Signed-off-by: William Wu <william.wu@rock-chips.com>
uart2 is used by fiq debugger, and we use ttyFIQ as console,
so do not enable uart2, or it enable ttyS2 as console.
Change-Id: Ib1b01f14c553da75830efa5b4e11933ef997e446
Signed-off-by: Liang Chen <cl@rock-chips.com>
For PMIC that power off supplies by write register via i2c bus,
it's better to do power off at syscore shutdown.
Because when run to kernel's "pm_power_off" call, i2c may has
been stopped or PMIC may not be able to get i2c transfer while
there are too many devices are competiting.
This patch effects on PMIC: RK808/RK818/RK816, not including RK805
which power off system by pull up pmic sleep pin in ATF.
Change-Id: I2eb139f75abf32a9c239b56a8e65e76c42927e87
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
When PMIC irq occurs, regmap-irq.c will traverse all PMIC child
interrupts from low index 0 to high index, we give fall interrupt
high priority to be called earlier than rise, so that it can be
override by late rise event. This can helps to solve key release
glitch which make a wrongly fall event immediately after rise.
Change-Id: Ieda1d6fd3c50cc36742a4740504ec7ce12ea509b
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Even "rockchip,system-power-controller" is not found,
rk808_i2c_client is needed for suspend/resume and the
other.
Change-Id: I17ebb3a1d1e7ec8dc9f4a3ee2dbdcd9ae4c1648b
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
set 3.4v interrupt signal assert when suspend, set 3.0v shutdown
signal assert when resume.
Change-Id: Id15b721bbdc9665a18cf9946b92c435a23f1666c
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
set 3.4v interrupt signal assert when suspend, set 3.0v shutdown
signal assert when resume.
Change-Id: Ie91d8ce6a79e5ea50b654ea52c3ed8acf047f8fb
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
