DP firmware uses fixed phy config values to do training, but some
boards need to adjust these values to fit for their unique hardware
design. So get phy config values from dts and use software link training
instead of relying on firmware, if software training fail, keep firmware
training as a fallback if sw training fails.
Change-Id: I075bff6aa153a5e18b6a5ddec2645131f1411913
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
The drm_dp_link is removed. And link.num_lanes is instead by
max_lanes. Link.rate is instead by max_rate.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I95cbaa541bdf28133ab86f46ce3ac9f0903d364d
Use wait_event_interrupt to replace wait_event_timeout.
The task irq or task work timeout will wake up the session wait.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I47254ca0e66b210d91578b24d63578f9ea5308f9
On the RK3562 SoC, the HPLL is designed dedicated for audio.
This patch assigns PLL_HPLL as the parent of digital audio
interface default. and Set PLL_HPLL to 983.04M(48k group)
default to achieve better jitter performance.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I21615ae46209a2be31630987350131abd3b33a97
Currently, the BCLK/FSYNC enable is addressed in hw_params
stage, because the real clk is measured by samplerate. so,
it is quite a good solution.
But, on the system PM situation, it is failed to recovery
BCLK/LRCK after resume. the root cause is that never do
'hw_params' after resume. which is similar to XRUN issue.
So, let's move it to prepare stage which any path must do
before trigger-start.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I9025a98259a4e9bd9f09ec3d23584f753552031d
This patch use the generic pm_runtime_force_* API for system PM,
because both of them do the same action. let's make it implemented
with runtime PM.
Ref: commit 37f204164d ("PM: Add pm_runtime_suspend|resume_force functions")
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ice5057ca5cdf8999990283a99921b7b6a30cd557
1. NV12/NV16/YUYV xoffset must aligned as 2 pixel;
2. NV12/NV15 yoffset must aligned as 2 pixel;
3. NV30 xoffset must aligned as 4 pixel;
4. NV15/NV20 xoffset must aligend as 8 pixel at rk3568/rk3588/rk3528/rk3562,
others must aligned as 4 pixel;
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I28d69d1f8189963170ef798c12bfd60fb092ef20
Enable the maxim max96772-based panels used on RK3588 vehicle s66 project.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I2065012318aab045c91500c7f9691bd9bee1007a
logical and physical nodes are separated, one logic node can
connect multi hw node
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: Ibb75cc466452aedff8f50d29331b191d2fbd922a
1. all logic node of mipi phy can get all hw of mipi phy
2. the links between logic and hw is determined by upper level equipmen
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: Icc0cb88c3294a119431ac24b0043e44e34b1b292
set HSTX_CLK_SEL 1`b1 when cphy lane rate under 500Msps,
while set HSTX_CLK_SEL 1`b1 when dphy lane rate under 1500Mbps
Change-Id: Ic42ce385c1952febe0327594231f6bffb2543c5e
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
The voltage domain of the usb2 phy grf interrupt mask
register usually belongs to the VD_LOGIC in most of
Rockchip SoCs. So if the VD_LOGIC is power off after
system suspend, the configuration of the usb2 phy grf
interrupt mask may lost when resume.
Test on RK3588 platform with micro usb2.0 interface,
if this case happened, the usb device failed to connect
to host, because the usb device depends on the bvalid
irq to start the enumeration.
This patch enable the bvalid detect irq upon resume
for otg port, and schedule the otg sm delayed work
if the bvalid is high which means that usb device has
connected to Host.
Change-Id: I29245ec4fc812e45eb3f52cc5c2c270b659a0cc6
Signed-off-by: William Wu <william.wu@rock-chips.com>
The legacy api drmModeCrtcSetGammalegacy can be called independently, so it need extra config done;
and the atomic api have config done at the vop2_crtc_atomic_flush();
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Idca4c42f1d298ec312dc839ee526e4132d9d8b73
1. config vp1 pre_dither_down at split mode;
2. disable pre_dither_down at YUV 10/8 bit output and RGB 10 bit output;
3. enable pre_dither_down at RGB 8/6 bit output;
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I304fc66324c97e3e4f50e03b8c8c2c1835871b1a
