Reorder system heap pages by bit[14:12] of pages' physical address, it
benefit for dram do access in different banks once time.
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I686c9e54f456d3b7f373ab1b0586125e70f891ec
Two axi bus:
AXI0 is a read/write bus with a higher performance.
AXI1 is a read only bus.
Every window on a AXI bus must assigned two unique
read id(yrgb_id/uv_id, valid id are 0x1~0xe).
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I867df219797da33f89fec6fba639bcdf55cb54b3
Support the system_heap to allow cpu access partial dma-buf.
Change-Id: I8250c0bb26b776b8c8f5e4c3ee0cb71e26445743
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Add DMA_BUF_IOCTL_SYNC_PARTIAL support for user to sync dma-buf with
offset and len.
Change-Id: I03d2d2e10e48d32aa83c31abade57e0931e1be49
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Bt command think if EL0_SP is less than 0xffffffcxxxxxxxxx
it is user mode, but EL0_SP may be 0xffffff8xxxxxxxxx.
According to ARM-V8, the virtual address bit63 determine
TTBR0 OR TTBR1. So if EL0_SP is less than 0x8000000000000000,
it is user mode.
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: Ib97b405df6e669e3806161c97801847e2f5d247a
The controller must route to the comboPHY when it works.
pcie1l0_sel
Select the signal form PHY to PCIe1l0
1'b0: Select comb PHY
1'b1: Select PCIE3 PHY
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I5e7faf71fdd22958c757f884f75ec9a00aeb2fb9
Add dts decode to support the pcie2x1l0 and pcie2x1l1 setting, which is
in PHP_GRF_PCIESEL_CON.
pcie1l0_sel
Select the signal form PHY to PCIe1l0
1'b0: Select comb PHY
1'b1: Select PCIE3 PHY
Usage in dts:
rockchip,pcie1ln-sel-bits = <0x100 0 0 0>;
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I5fb177f37b23c5f3cdaadf8c103f8e6487ea6a76
Currently, the datasheet and pcb design has removed all the
pin {bclk, lrck}_rx, and use the pin {bclk, lrck}_tx only
to simpilify design.
- Remove pin {bclk, lrck}_rx
- Rename pin {bclk, lrck}_tx to [bclk, lrck]
So, we do the same thing by default.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ide90500b766fa39d6f032b0edf309e001939b579
Currently, the datasheet and pcb design has removed all the
pin {bclk, lrck}_rx, and use the pin {bclk, lrck}_tx only
to simpilify design.
- Remove pin {bclk, lrck}_rx
- Rename pin {bclk, lrck}_tx to [bclk, lrck]
So, we do the same thing by default.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ief06364337ccd6b7f2bc61ffd4aeb8d6e168a8a4
Enable the ELAN touch panel used on Rockchip RK3588s tablet.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ia93230ac356752600ea98182cc0b26ae4320c094
drivers/input/touchscreen/elan/elan_update.c:40:22: error: incomplete definition of type 'struct i2c_client'
Fixes: 7f61b3481d ("input: touchscreen: support ELAN TP_5515")
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I9b5aa8c8fc5d6ee2082938dc74719a2db9041f9d
Enable this to support RK3588 GPU.
But RK3568 GPU should disable this config.
Signed-off-by: Zhixiong Lin <zhixiong.lin@rock-chips.com>
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
Change-Id: I78c165329c9cbc8565af26494c6034dcc704ad66
Enable the ELAN touch panel used on Rockchip RK3588s tablet.
Signed-off-by: Jianhui Wang <wjh@rock-chips.com>
Change-Id: I4a5f116cd8bfd9e6cb232af9f4eabe9289978372
This bit has a hide founction for height/low bit swap,
And should not be touched.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I8ce2caddebdf87edbd75cc1fe4460699e7d9ca89
Video_Pixclk = edp_pixclk x K = edp_dclk x K = dclk_core x 4;
K = 2 for SPLIT, other condition is 1.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I8e6f3e32bd1c214bfe46cc3f37dd813af8901839
