Use DOMAIN_RKXX_PROTECT to keepon the pd during startup.
Change-Id: I526b97ec273e056e703b6e187d0e6ffec44e730c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This bit enables the automatic mechanism to stop providing clock in
the clock lane when time allows.
Change-Id: Ia3d85589f54adcf6206ee7ded32624b8e92936af
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Three operating mode are available to convey the graphical data
to the display:
- Video mode streams over the high-speed link the RGB data and the
associated synchronization signals directly generated by the LCDC.
The streaming starts as soon as the DSI Host and the LCDC are enabled.
This continuous refresh is the best way to interface with a display
without Graphics RAM.
- APB command mode sends commands over the high-speed link for
configuration as it is done using a legacy serial interface (SPI).
The commands are launched using the DSI Host APB interface.
- Adapted command mode is the best way to interface with a display
having its own internal Graphics RAM. The DSI Host captures only
one full frame coming from the LCDC and transforms it into a series
of write commands to update the display Graphics RAM.
Change-Id: Id2a9ccf71997f42126a3719bc349576013970158
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
In order to enhance the overall robustness of the system, DSI defines
a dedicated EoT packet (EoTp) at the protocol layer for signaling
the end of HS transmission. For backwards compatibility with earlier
DSI systems, the capability of generating and interpreting this EoTp
can be enabled or disabled.
Change-Id: Iddc7e82a7e3e47dea94846fbb771da8fddc0fda3
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Add full support for MIPI DSI Processor-to-Peripheral transaction types.
Change-Id: Ic0ebb55908c95541b7356d4796869202aa3ffcdc
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Since msleep is based on jiffies the panel could take longer
than expected. So use msleep for values greater than 20 msec
otherwise usleep_range.
Change-Id: Ib03c6e381b44a31dd57aeaaa3a88a459578de313
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This patch adds a new RGB media bus formats that describe
18-bit samples transferred over an LVDS bus with three
differential data pairs, serialized into 7 time slots,
using standard JEIDA data ordering.
Change-Id: Ia0bedd53e57aa34829a0d61b144aa99a1c98cffd
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
When enable display on loader, init gpio would change
gpio status, that would make screen flash.
Change-Id: I4b69a8d3d83c5bef09014c2134abaee6522a7046
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Some old code has too many conflicts with the upstream code,
so recombine and commit these changes.
Including these changes:
1.Support yuv420.
2.Limit rk3229/rk3328 max output resolution.
3.Support dynamically get input/out color info.
4.Introduce mpll_cfg_420.
5.use drm_mode_is_420 instead of DRM_MODE_FLAG_420_MASK.
Change-Id: I42462284b16f26b7adef0e9455903ee5fc71e432
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
iommu driver probe will register vop pd to power domain control, this pd
will be closed before display driver enable and lead to display black.
so we move vop pd to display driver control.
Change-Id: Ie25c20e79c57c4e1bc678774ad09b60fc4a135da
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
I found if eDP_AVDD_1V0 and eDP_AVDD_1V8 are not been power at
RK3288, once trying to enable the pclk clock, the kernel would dead.
This patch would try to enable them first.
The eDP_AVDD_1V8 is used for eDP phy, and the eDP_AVDD_1V0 are used
both for eDP phy and controller.
Change-Id: I4e8a34609d5b292d7da77385ff15bebbf258090c
Signed-off-by: Randy Li <ayaka@soulik.info>
Signed-off-by: Randy Li <randy.li@rock-chips.com>
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Add the ability to parse panel-desc data from the devicetree if it's
not hard-coded data.
Change-Id: I474940282657c9aa03568b9f98916125784d9fcf
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
The video BIST function of the DP_TX generates arbitrary video formats
internally according to the specified format configuration and selection.
These BIST video formats simplify DP_TX debugging.
Change-Id: Ia019c8f40fdd4ebea3e5250be8e2c15540481a6c
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Sometimes, we would abort suspend work before it finished.
In this case, suspend work would try to resume the part suspended
by correspond resume functions.
But the suspend/resume functions are not matched in rockchip.
When the suspend work is aborted, it would ignored resuming this
part due to can't find correspond resume functions.
So, let's use suspend_late instead of suspend.
Change-Id: I7304f7963704de7e870fbd4e76ebe1e0066f18c1
Signed-off-by: zain wang <wzz@rock-chips.com>
VOP output mode and bus_format must be ROCKCHIP_OUT_MODE_YUV420
and MEDIA_BUS_FMT_YUV8_1X24 when display mode has a YCbCr420
flag.
Change-Id: Ib2d51c119f5a8f1b8a9285c47ab228b22a293d56
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
