Add compatible string for Rk3528 gmac, and constrain it to
be compatible with Synopsys dwmac 4.20a.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I63d79df0812b5d2a40664aadc1ae36e6b2f9534a
Add constants and callback functions for the dwmac on RK3528 Soc.
As can be seen, the base structure is the same. In addition, there
is an internal phy inside with Gmac0.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I8a69a1239ed3ae91bfe44c96287210da758f9cf9
Use a common interface to implement power up/dowm for FEPHY,
which we could reduce codes.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ia7b42862abb20ea7395d6dad021621c8e1ededb9
This patch enable SAI which act as I2S/PCM/TDM, and much more
flexible protocol.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ie1295825040ebbd9dd3848ed1c961f616e52a60f
This patch enable SAI which act as I2S/PCM/TDM, and much more
flexible protocol.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I14b5f0ba183dddfdb97cf3365057e08201487d7c
Set dma maxburst per FIFO waterlevel for better performance
on high bit-rate situation, such as 192k 8ch 32bit situation.
Change-Id: Ida94609185b97c31bbfbb02ed65961c90f3d30f3
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This patch allow driver to set lanes auto depends on
common-use format, such as I2S, DSP_A, DSP_B etc.
And allow user to select lanes manually as required,
such as TDM32 x 4
Change-Id: If6adb2bded38faa3462c52286602506f991cc0e5
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This patch add the lost registers into W/R/V filter.
Change-Id: Ia731f261554ddecc846f80b3c13dbf2d7b009f12
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
The xHCI specification 1.1 does not require xHCI-compliant
controllers to always enable hardware USB2 LPM. However,
the current xHCI driver always enable it when seeing HLC=1.
On rv1106 platforms, the xHCI USB2 LPM is enabled by default.
And we found that a lot of USB Disks have USB2 HW LPM broken
issue when connected to rv1106 USB2 OTG interface.
Here are a part of special USB Disks with USB2 HW LPM broken:
1. idVendor=325d, idProduct=6410, Manufacturer: aigo
2. idVendor=21c4, idProduct=0cd1, Manufacturer: Lexar
3. idVendor=0951, idProduct=1666, Manufacturer: Kingston
When use dd command to write to these USB Disks, it may fail
with the following log:
[ 2844.700148] usb 7-1: reset high-speed USB device number 4 using xhci-hcd
[ 2889.072272] usb 7-1: reset high-speed USB device number 4 using xhci-hcd
[ 2921.498045] usb 7-1: reset high-speed USB device number 4 using xhci-hcd
......
[ 2953.923773] usb 7-1: reset high-speed USB device number 4 using xhci-hcd
Theoretically, we can add USB_QUIRK_NO_LPM individually for
these special USB Disks, however, it's difficult to cover all
USB Disks. So it's better to disable the USB2 LPM for xHCI
on rv1126 platforms.
Change-Id: Ideafe2ecf91fe3013825a064631509eecdad0254
Signed-off-by: William Wu <william.wu@rock-chips.com>
clk_get_rate()/regulator_get_voltage() maybe not useable when panic.
This reverts commit bc2d913a39.
Change-Id: I127a24cb596e459f9f608a5e2847b41530062758
This driver is modified to support RK3528 SoCs.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: If024916eb7b52ec86ff7533aedefc1bda457b612
According to a description from TRM, add all the idle request.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I3c58c73a61bf88d91930f9f3464207f820965b94
Add the clock tree definition for the new RK3528 SoC.
gmac1 clocks are all controlled by GRF, but CRU helps to abstract
these two clocks for gmac1 since the clock source is from CRU.
The io-in clocks are module phy output clock, gating child
clocks by disabling phy output but not CRU gate.
Add gmac0 clocks.
They are all orphans if clk_gmac0_io_i is not registered by
GMAC driver. But it's fine that GMAC driver only get it but
not to set/get rate.
Add CLK_SET_RATE_PARENT for mclk_sai_i2s0/1.
Allowed to change parent rate.
Add CLK_SET_RATE_NO_REPARENT for dclk_vop0.
dclk_vop0 is often used for HDMI, it prefers parent clock from
clk_hdmiphy_pixel_io for better clock quality and any rate.
It assigns clk_hdmiphy_pixel_io as parent in dts and hope not to
change parent any more.
Add CLK_SET_RATE_PARENT for aclk_gpu.
Allow aclk_gpu and aclk_gpu_mali to change parent rate.
Add CLK_SET_RATE_PARENT for aclk_rkvdec_pvtmux_root.
Allow aclk_rkvdec_pvtmux_root and aclk_rkvdec to change parent rate.
set aclk_m_core = core_clk/2.
aclk_m_core signoff is 550M, but we set div=2 for better
performance.
Add CLK_IS_CRITICAL for clk_32k.
Mainly for pvtpll during reboot stage.
Add CLK_IS_CRITICAL for all IOC clocks.
IOC doesn't share clock with GRF. The iomux can't be changed if they
are disabled.
Disable aclk_{vpu,vpu_l,vo}_root rate change
They are all shared by multiple modules, disable rate change
by modules.
Don't register clk_uart_jtag
It's for force jtag uart delay counter. It must be open
for box product without tf card but with uart0.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I09745b6a31484d6a27f04e608268d9738c1fe224
Add the dt-bindings header for the rk3528, that gets shared between
the clock controller and the clock references in the dts.
Add softreset ID for rk3528.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I465f0a3c7fc36eee4c2ab0de38a810b8e691d41e
clk init is only used at rk3588 but rk3528 version is bigger
then rk3588
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I0730242f223b6ab3b48765c13fe4ff1ab2803570
Add branch_gate_no_set_rate for gate clks not
allowed to support setting rate.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Ic940acbc035804a011e59b8e1a0d440168e18c26
