Enable the HDPTX PHY driver used on Rockchip RK3588 SoC.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ib96cd35d7bda166900afc4b0650f922a21f1c0d5
Add a new driver for Samsung HDPTX Combo transmit-PHY IP used
in Rockchip RK3588 SoC. The HDPTX is a PHY hardmacro to
support HDMI and DP interfaces.
Currently, it supports only DP mode.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ie70017969ee59dfc53f9e319591aa3f998a86b0c
This patch adds support for sound which link multiple codecs
to the same cpu dai.
Change-Id: I77d3e9c10d03c2b8809c6d82b5268dba279ee6f0
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This patch adds compatible string for rk3588 vad.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I69672704997a9344faa6b53b050e82d6259afdfd
1) make ARCH=arm64 savedefconfig
2) Enable CONFIG_PRINTK_TIME_FROM_ARM_ARCH_TIMER
For get boot time better
3) Enable CONFIG_RFKILL_RK
4) Enable CONFIG_SND_SOC_ES8323
This patch enable CONFIG_SND_SOC_ES8323 default for rk3588 evb boards.
5) Enable CONFIG_PHY_ROCKCHIP_SAMSUNG_DCPHY
The driver is used by RK3588.
6) Enable type-c support
Select Type-C related configs for Rockchip SoCs.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: I42144dcb9ffbaced8ca58acc786c7319e6116a7b
This patch add usb3 combphy for usb3 host_2, with this
patch, the rk3588s evb2 board can support usb3 host.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Ia8fdf5921218a554bb29ab4a8cc10fbd1b37827d
This patch add usb3 combphy for usb3 host_2, with this
patch, the rk3588 nvr demo v10 board can support usb3 host.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I72301e14fc6b428722f171795377b1cbae9d2aa4
This patch add usb3 combphy for usb3 host_2.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I38fb63446a285d791cd0466e112ad33df1f3254e
This adds a new USBDP combo PHY with Samsung IP block driver.
The driver get lane mux and mapping info in 2 ways, supporting
DisplayPort alternate mode or parsing from DT. When parsing from DT,
the property "rockchip,dp-lane-mux" provide the DP mux and mapping info.
When do DP link training, need to set lane number, link rate, swing, and
pre-emphasis via PHY configure interface.
Change-Id: I84256746c28d98efcadff5998bfb35a28c959410
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Add device tree binding document for Rockchip USBDP Combo PHY
with Samsung IP block.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: Id9924e8061881ada6d5d2c2a36feb5009a85487b
This patch adds support for Analogix eDP TX IP used on RK3588 SoC.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I362489fb294673512b6de1913aa2e0b855a98926
The wrong choice is at GMAC1 RGMII delayline control.
Fixes: 2627dcd2c9e9("net: ethernet: stmmac: dwmac-rk: Add gmac support for rk3588")
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ibc31f4f8b0f8c23c7ca3b290f3d95ba34f03c05f
This is required by android hwc for dev/dri/card128.
Change-Id: Ia0159b877f7d8b2bb5cecf3b352b67d9c76c7c97
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
1. support buffer_size set by user
2. support assigned chn
3. support udma read
4. support buffer address set by userspace
Need to update test_pcie and test-pcie-ep-new.
New test command:
1. run ./test-pcie-ep-new 500 1024 chn_num buffer_address both on RC and EP first
Release buffer use dma channel number = chn_num.
if buffer_address = 0
pcie_dma_buffer_address get from DT reserved memory
else
pcie_dma_buffer_address = buffer_address
2. run ./test-pcie 1 1000 1024 1 chn_num on RC
The last "1" means enable PCIe udma read, "0" means write.
RC read from EP use dma channel number = chn_num.
3. run ./test-pcie 2 1000 1024 1 chn_num on EP
EP read from RC with offset = buffer count * buffer size.
4. check version by:
cat /sys/kernel/debug/pcie/pcie_trx | grep version
5. 1024 means set buffer size to 1MB.
Change-Id: I7613037924659c75014d19b6c4845e096a56d295
Signed-off-by: Simon Xue <xxm@rock-chips.com>
These controllers use the same clk for tx/rx.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ie9a0adb950cdc584761c1079cb45e58d5eafccfb
Reserved 8M for cma heap, the node' name will be used as heap' name.
Also add ramoops and logo node.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I50654b1122126bb54092e3933d1a36cadf8d4ec5
When enter low temperature mode, system monitor update opp table, then
check and change the current voltage for cpu, but now the opp voltage
inside cpu_opp_helper() may be old, the current voltage may be changed
back to old value. Move the volt_adjust_mutex out of dev_pm_opp_set_rate()
so that the opp voltage inside cpu_opp_helper() will be latest.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I9a91775dc9b5443e4b47b4255de6e21133c32404
If read multiple channels at the same time, channel 1 will
error, add assert when start saradc as a workaround.
Change-Id: Iababf604b200555a46a96e1ca0bc7108c6df8680
Signed-off-by: Simon Xue <xxm@rock-chips.com>
The RK3588 SoC has seven channels TS-ADC(TOP, BIG_CORE0, BIG_CORE1,
LITTEL_CORE, CENTER, GPU, and NPU).
Change-Id: I940a10c8062ba73876f2dfd133ab8ea60ad3a799
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
