When a mst capable immediate downstream device connected,
some workqueue is used to help build and menage the
topology, write/read sidband message. To avoid some access
aux issue happen. we config phy power on when mst capable
immediate downstream device connected and config phy power
off when it becom disconnected.
When a mst capable immediate downstream device connected
and enter to suspend state, it need config phy power off.
And it need config phy power on when it enter to resume
state. This operation to guarantee phy can really power
off when suspend and really power on when resume.
Change-Id: I50e9c800c7b07ea2dd00d8728e08e9abc687378f
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
1. use rockchip,split-mode instead of split-mode;
2. rockchip,split-mode is split two same display interface and
register one connector;
3. rockchip,dual-connector-split is split two different display interface and
register two connectors;
4. use rockchip,left-display to identify the left display.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: If428796d5bd36f6504b10faa31f8c74d73ff6036
1. use rockchip,split-mode instead of split-mode;
2. use rockchip,dual-channel instead of dual-channel;
3. rockchip,split-mode is split two same display interface and
register one connector;
4. rockchip,dual-connector-split is split two different display interface and
register two connectors;
5. rockchip,dual-channel use two same display interface to driver
one two channel panel and register one connector.
6. use rockchip,left-display to identify the left display.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ieb4519d1185a978a35fbdbeafc6fe1ac68e2328b
1. use rockchip,split-mode instead of split-mode;
2. rockchip,split-mode is split two same display interface and register
one connector;
3. rockchip,dual-connector-split is split two different display interface and
register two connectors;
4. use rockchip,left-display to identify the left display.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I425f80951fd5c99b31aa250383384500bae5f5f5
Find the physical ID based on the logical ID of the CPU. Currently,
there are three possible order of physical CPU IDs:
1.Typical RK3588 platform: 0 1 2 3 4 5 6 7.
2.RK3588 NVR SDK swap cpu: 4 5 6 7 0 1 2 3.
3.RK3583: 0 1 2 3 4 5 or 0 1 2 3 6 7.
Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com>
Change-Id: I174c06afb143f05e07b4d277a487383c3119938f
The original version would hold the DRM lock and immediately do a
drm_atomic_commit(), which may result in significant loss of
performance.
This patch postpones the commit timing. When the DRM commit has
taken effect, no additional commits will be made.
Change-Id: I04843e5ff490152fb53a967ed3fbd2e010d84ed6
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
The pixel shift feature allows to specify an X and Y direction offset
and apply offset to all planes.
Specify the vp to enable the feature in the dts:
&vp1 {
rockchip,pixel-shift-enable;
};
Offset values can be specified in user space:
echo shift_x shift_y > /sys/class/drm/card0/video_portX/pixel_shift
The "X" in "video_portX" corresponds to the video port id.
Change-Id: I96d3bc5bc21114621606cb38243dfc015c5f8ba3
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
This patch creates device nodes for each available crtc:
/sys/class/drm/card0/crtc_name
Change-Id: I748f56d90c3781b6e3100dfd08b4070ee7212575
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
* Add state init on prob and reset
* Fix implicit declaration of function 'rockchip_uninit_opp_table' for kernel 5.10.160
* Add nbuf sgt support
Signed-off-by: Felix Zeng <felix.zeng@rock-chips.com>
Change-Id: Ibb88d88709ba5dea7debaafa44deb206c9a1f1af
The original pipe_phystatus reg configuration only
set the bit[3:2] (GRF control usb pipe phystatus)
for usb2.0 only interface. It's effective for usb2
device, but it's imperfect for usb2 host mode. In
order to support usb2 host mode, this patch sets
the whole bit[15:0] which include disable u3 port
and select utmi source clock.
Change-Id: I5cde52da2c6e170885df6c4a59f6785e1c485df7
Signed-off-by: William Wu <william.wu@rock-chips.com>
If the uboot logo is enabled, it is needs to obtain the pll frequency
set in the uboot during phy probe. If uboot logo is disabled, it is
need to set a default frequency when enable hdmiphy pll for the first
time.
Change-Id: I566d361a4864324ef4071d9764d84a0fde7d88ee
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Fix bug:
There is a hw bug, the encoder has probabilistically encodes
one frame repeatedlly and does not return enc done in time.
Solution:
Through special config and check the slice done interrupt can determine
that encoding is done and safe reset the rkvenc.
Change-Id: I1a3511523636eac94a9cf89b15cb95b87c447154
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
The default 2-div autocs of vop will cause display abnormal when
multi-pannel with high resolution, so set default div to 1 and
vop driver will take over later.
Signed-off-by: Liang Chen <cl@rock-chips.com>
Change-Id: I6ab9db00ea2cacfdecdb167b7ad67063c25108b1
The power domain of the usb grf belongs to PD_USB
on both RK3576 and RK3588 platforms. The PD_USB is
managed by the USB controller driver, and it maybe
powered down if USB is not working.
Test on RK3576 EVB2 which supports Type-A USB3.1 +
DP 2xLanes, connect DP to Display screen, meanwhile,
USB not used, SError happens with the following log:
[ 224.958079][ C0] Kernel panic - not syncing: Asynchronous SError Interrupt
[ 224.958084][ C0] CPU: 0 PID: 132 Comm: kworker/0:2 Tainted: G O 6.1.57 #11
[ 224.958089][ C0] Hardware name: Rockchip RK3576 EVB2 V10 Android Board (DT)
[ 224.958092][ C0] Workqueue: events dw_dp_hpd_work
[ 224.958101][ C0] Call trace:
[ 224.958103][ C0] dump_backtrace+0xf4/0x114
[ 224.958115][ C0] show_stack+0x18/0x24
[ 224.958122][ C0] dump_stack_lvl+0x6c/0x90
[ 224.958132][ C0] dump_stack+0x18/0x38
[ 224.958137][ C0] panic+0x14c/0x338
[ 224.958145][ C0] check_panic_on_warn+0x0/0x90
[ 224.958155][ C0] arm64_serror_panic+0x68/0x74
[ 224.958160][ C0] do_serror+0xc4/0xcc
...
[ 224.958218][ C0] regmap_write+0x54/0x78
[ 224.958224][ C0] udphy_power_on+0x16c/0x1b0
[ 224.958233][ C0] rockchip_dp_phy_power_on+0x58/0x1bc
[ 224.958240][ C0] phy_power_on+0x8c/0x108
[ 224.958248][ C0] dw_dp_bridge_detect+0x58/0x348
[ 224.958256][ C0] drm_bridge_detect+0x28/0x34
[ 224.958264][ C0] dw_dp_connector_detect+0x34/0x4c
[ 224.958272][ C0] drm_helper_probe_detect+0xd0/0x1a0
[ 224.958281][ C0] check_connector_changed+0x50/0x1b0
[ 224.958288][ C0] drm_helper_hpd_irq_event+0x78/0x134
[ 224.958295][ C0] dw_dp_hpd_work+0x58/0x818
This patch moves udphy_u3_port_disable() from the
udphy_power_on() to rockchip_u3phy_init(), it can
avoid access usb grf during dp phy power on, and
the rockchip_u3phy_init() is called from the USB
controller driver, this can make sure the PD_USB
is powered on if it access usb grf in the USBDP
PHY driver.
Change-Id: I434b2efbbbb5b513ec668bca1c8800d0f7f18e12
Signed-off-by: William Wu <william.wu@rock-chips.com>
Detecting the hpd irq in the gpio irq handler, the hpd
type will overwrite by the next gpio irq. So the hpd work
can't recognize the hpd irq.
Use a state machine to deal with the hpd status to avoid this
issue happen.
Change-Id: I1214b1a281cbb8e82431bcc1c2b4a0856d64a7a0
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
set vop aclk mode to ROCKCHIP_VOP_ACLK_RESET_MODE is better
for power and performance.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I8514e57af6ac8950112a6c675f5eb03fe4e44cf0
The VOP Lite unit is found on rk3576 which use legacy VOP architecture.
Change-Id: I800523a7dac1e086db26b3fbf731f3d07e1ed68d
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
To save mcr value when uart is reset for setting baudrate.
Change-Id: I1a4fcd78498cf4f601d0c8461d1db67dc0ed6f9e
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
The wrong value will make irq counter stop to increase at 200001, and
software takes more time to finish encoding.
Fixes: 53048fad2a ("video: rockchip: mpp: Add JPEG VPU720 driver")
Signed-off-by: Johnson Ding <johnson.ding@rock-chips.com>
Change-Id: Id98fcdc6d4e617e8dfba1bc6471295a14c48594b
VOP YUV overlay only can support YUV limit range, so force select BT601L
todo R2Y.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I3af0d916d549a1fd890f14d3723f3264c779a1ea
Plane csc determines its own color input path on the input
color format of plane. So when DCI is enabled should force
yuv csc path.
Change-Id: I66d5f3e773fc0fd631673622c22b242dcc791afe
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
1.Delete the assigned-clock
2.Only rely on spi-max-frequency configuration in sub nodes
Change-Id: I040a3afaa0c92de854f9f21eb58e912d6638b080
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
1.Delete the assigned-clock
2.Only rely on spi-max-frequency configuration in sub nodes
Change-Id: I952376e0e898635dda299c833759a84efbe631cf
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
