It comes from the result for SD3.0 test that level 5 is
suitable for this platform.
Change-Id: I95da7be6f514367799ea5e8e7c4b338fd1b1435e
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
This patch allows user to set I2Sx_MCLKOUT rate
by CLK_SET_RATE_PARENT.
Change-Id: I2248d67e24159886b266d6f024026f402a50747b
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Add a compatible string for the eDP controller found in the RK3568 SoC.
Change-Id: I4ece0815efd7d603ee0c5f5adac8d3bf5b91130e
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This patch adds support for Analogix eDP TX IP used on RK3568 SoC.
Change-Id: Ieb89906cba5bc569ed8c476fecd00f6035a7f582
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
The Linux rootfs allow to be readable and writable by default.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: Ibc8de371c2b27a5062311e079bfe3389c5ffd6c8
Enable the eDP PHY driver used on Rockchip RK3568 SoC.
Change-Id: I7cf7509e66e660facf98f906e238e311e9cc4f54
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Add DT binding documentation for Naneng eDP Transmitter PHY IP used
in Rockchip's RK3568 SoC.
Change-Id: Id45165ccaef7d82f590e8d6ff26c6b6a0784314f
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
DPTPHYT22ULP is designed for chips that perform eDP/DP data
communication while operating at low power consumption.
The main link is a multi-gigabit transmitter macro which
enable speed up to 4.0Gbps data transmitter with optimized
power and die size, also it can be easily fabricated and
implemented in a video system. The AUX channel is a halfduplex,
bidirectional channel consisting of one differential pair,
supporting the bit rate of about 1Mbps.
Macro consists of multi-main link transmitter channels,
AUX channel, one PLL and bias-gen unit. The main link
transmitter performs dedicated P2S, clock generator,
driver with preemphasis and self-test. Each of the channels
can be turned off individually.
Change-Id: Idf58991ff1bdd4557c4cfadf2dc047e95eca7668
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Allow DisplayPort PHYs to be configured through the generic
functions through a custom structure added to the generic union.
The configuration structure is used for reconfiguration of
DisplayPort PHYs during link training operation.
The parameters added here are the ones defined in the DisplayPort
spec v1.4 which include link rate, number of lanes, voltage swing
and pre-emphasis.
Add the DisplayPort phy mode to the generic phy_mode enum.
Change-Id: Id68cbd69c0938bd64402b8af7b6b37b168472848
Signed-off-by: Yuti Amonkar <yamonkar@cadence.com>
Reviewed-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(cherry picked from commit 42d068472d)
Now that we have some infrastructure for it, allow the MIPI D-PHY phy's to
be configured through the generic functions through a custom structure
added to the generic union.
The parameters added here are the ones defined in the MIPI D-PHY spec, plus
the number of lanes in use. The current set of parameters should cover all
the potential users.
Change-Id: Ie5a12064ba59a1a2c8628bd34c4c2b4996559ec3
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(cherry picked from commit 2ed869990e)
The phy framework is only allowing to configure the power state of the PHY
using the init and power_on hooks, and their power_off and exit
counterparts.
While it works for most, simple, PHYs supported so far, some more advanced
PHYs need some configuration depending on runtime parameters. These PHYs
have been supported by a number of means already, often by using ad-hoc
drivers in their consumer drivers.
That doesn't work too well however, when a consumer device needs to deal
with multiple PHYs, or when multiple consumers need to deal with the same
PHY (a DSI driver and a CSI driver for example).
So we'll add a new interface, through two funtions, phy_validate and
phy_configure. The first one will allow to check that a current
configuration, for a given mode, is applicable. It will also allow the PHY
driver to tune the settings given as parameters as it sees fit.
phy_configure will actually apply that configuration in the phy itself.
Change-Id: I252cb7733740a28728e9ff228cba9a6b407b1b07
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(cherry picked from commit aeaac93ddb)
With this patch, the pinctrl driver will support output-high/ -low
pinconf, which passed from dts iomux nodes.
So the pinctrl module needs the gpio_chip which registered by gpio
module.
This patch makes the gpio driver use the rockchip_pin_bank from pinctrl,
after that, the pinctrl can call the gpiolib operations, include output.
Also do iomux check before call gpiolib operations, make sure that the
pin hasn't been used as other functions.
Change-Id: Iaba6f1ade8494235586d5e5ce52d6d497e072bc4
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
DesignWare based SDHCI controller will be used for eMMC on some
Rockchip platforms such as RK3568.
Signed-off-by: Hans Yang <yhx@rock-chips.com>
Change-Id: Icfc6b06d92267114bac44b06db96c923befee499
