After commit cdc6f7d0b0 ("media: remove unused video drivers"),
these files are unused, so just remove them.
include/media/camsys_head.h
include/media/v4l2-chip-ident.h
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ib561e90ec55f8f2b51c6d5fe3e03fe25836e511e
Add no-sdio/no-sd for emmc; no-sdio/no-mmc for sdcard; no-sd/no-mmc for
sdio.
Change-Id: I13d3918f41f63ed9b27e9969e6f89d1006c9d45c
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
According to the dwc2 programmer's guide v3.10a, in '2.1.3.2 Dedicated
FIFO Mode with No Thresholding', it suggested that:
Device RxFIFO =
- Scatter/Gather DMA mode:
(4 * number of control endpoints + 6) + ((largest USB packet used / 4) +
1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK
on rockchip platforms:
(4 * 1 + 6) + ((1024 / 4) + 1) + (2 * 6) + 1 = 280
- Slave or Buffer DMA mode:
(5 * number of control endpoints + 8) + ((largest USB packet used / 4) +
1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK
on rockchip platforms:
(5 * 1 + 8) + ((1024 / 4) + 1) + (2 * 6) + 1 = 283
Device IN Endpoint TxFIFO =
The TxFIFO must equal at least one MaxPacketSize (MPS).
In addition to RxFIFO and TxFIFOs, refer to dwc2 databook v3.10a,
'Figure 2-13 Device Mode FIFO Address Mapping and AHB FIFO Access Mapping
(Dedicated FIFO)', it required that when the device is operating in non
Scatter Gather Internal DMA mode, the last locations of the SPRAM are used
to store the DMAADDR values for each Endpoint (1 location per endpoint).
When the device is operating in Scatter Gather mode, then the last locations
of the SPRAM store the Base Descriptor address, Current Descriptor address,
Current Buffer address, and status quadlet information for each endpoint
direction (4 locations per Endpoint). If an Endpoint is bidirectional , then
4 locations will be used for IN, and another 4 for OUT).
Considering that the total FIFO size of dwc2 otg is 0x3cc (972),
and we must reserve (4 * 13) = 52 locations for all Endpoints.
So reconfig dwc2 device fifo size as follows:
Device RxFIFO = 280
Device IN Endpoint TxFIFO
- FIFO #0 = (64 / 4) = 16 (Assuming this is used for EP0)
- FIFO #1 = (1024/4) = 256 (Assuming this is used for Isochronous)
- FIFO #2 = (512/4) = 128
- FIFO #3 = (512/4) = 128
- FIFO #4 = (256/4) = 64
- FIFO #5 = (128/4) = 32
- FIFO #6 = (64/4) = 16
After reconfig the dwc2 device fifo size, test mtp write on rockchip
platform (PC -> rockchip platform) on rk312x/rk3326/px30/rk3288 evb,
when mask the 'vfs_write' in f_mtp.c, the writing data rate can be
increased from 16MBps ~ 20MBps to 30MBps ~ 36MBps on different kinds
of rockchip evbs.
Change-Id: Icdf8a5dd95f96d174233e4ffc765c9a982b9f0b6
Signed-off-by: William Wu <william.wu@rock-chips.com>
Single entry is for target voltage and three entries are for
<target min max> voltages. Change cpu opp-microvolt form one entry to
three entries and set maximum acceptable voltage to a high value so that
regulator device can supply multiple consumers at the same time.
Fixes: 16e9353f89 ("arm: dts: rockchip: Change cpu opp-microvolt form one entry to three")
Change-Id: I96e5f87f2945e63e8f4a073fa0292f001830b13c
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This reverts commit 8c0aa0e3a3.
pm_test is unused.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I914e68dc412aea0ad5014be686c1f2579bd472a1
Clear irq status first then handle the udma interrupt.
Change-Id: I3638524b7bd09ad21a431bfebd3ba0b5bfbe7b8e
Signed-off-by: Simon Xue <xxm@rock-chips.com>
This reverts commit 8e4b2eda3f.
optee_linuxdriver is unused.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I5d092293ccbc26e77e16a141ffaff85020bb9aaa
This patch adds devicetree support to gmac of rk1808 with proper
devicetree compatible strings.
Change-Id: Id35523a10f987cbb9b9c33ad32ab23cb3c6d4e2b
Signed-off-by: David Wu <david.wu@rock-chips.com>
After the completion of Clause 37 auto-negotiation, xpcs automatically
switches to the negotiated speed for 10/100/1000M.
Change-Id: Iab9dd6ee61a35bf89fd3a0721f5d398de501a7ec
Signed-off-by: David Wu <david.wu@rock-chips.com>
The RK3568 has two gmac, but the driver only support one mac address
right now, define the more ethernet mac address at vendor storage to
support it.
Change-Id: If47df961136da6fe13ede1e5817717db2c0ad2f6
Signed-off-by: David Wu <david.wu@rock-chips.com>
Add constants and callback functions for the dwmac on RK3568 soc.
As can be seen, the base structure is the same, only registers
and the bits in them moved slightly.
Because there are two gmac controllers at rk3568, use
bus id to set the corresponding registers respectively.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I26e8dbc172c7c14df230f531251e2cd23d78a787
Add constants and callback functions for the dwmac on RV1126 soc.
As can be seen, the base structure is the same, only registers
and the bits in them moved slightly.
Because the gmac driver does not know whether pinctrl is
configured with m0 or m1 at this time, so we configure the
delayline of m0 and m1 at the same time.
Change-Id: I3bf58f30584f91c53dd98f747b2d5a2e3f32c505
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Use the phy_clk to prepare_enable and unprepare_disable related phy clock.
Change-Id: Idcf3ee00c03b4a5009a6a9385077b0a421dbc601
Signed-off-by: David Wu <david.wu@rock-chips.com>
The gmac5.10a configure has_gmac4 with true and has_gmac with false.
Others still stay has_gmac with true.
Change-Id: I0d0d1adef8551d2f7aac6702f963cb23a9861036
Signed-off-by: David Wu <david.wu@rock-chips.com>
Add constants and callback functions for the dwmac on rk1808 soc.
As can be seen, the base structure is the same, only registers
and the bits in them moved slightly.
Change-Id: I39a75b89cd17331bb4373b9b249ae206e1420e71
Signed-off-by: David Wu <david.wu@rock-chips.com>
Add constants and callback functions for the dwmac on rk3308 soc.
The base structure is the same, but registers and the bits in
them moved slightly, and add the clk_mac_speed for the select
of mac speed.
Change-Id: Ieaea3ade9e51d5118f0eb855d8e02febfb2275d1
Signed-off-by: David Wu <david.wu@rock-chips.com>
The MDC clock is divider from APB Clock for rockchip's socs, if it
was from mac_clk, the mdc clk range might not be between the frequency
range 1.0 MHz - 2.5 MHz.
Change-Id: I4e4fcb1be239a8d78a39fc1f4e2af5bb87258798
Signed-off-by: David Wu <david.wu@rock-chips.com>
This reverts commit f19114808f.
devinfo is unused.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I177ecd227330250bb33fc350cbe850a8cca5a751
because currently mclk is handled by codec side, so the
associated pinctrl should be handled by codec too.
Change-Id: I55db6e9a0181cae0cb414b9dcacae7ff0214b50c
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
The cpufreq cooling doesn't support calculating static power in 5.10
and the cpu and gpu opp table are changed.
Change-Id: Ia1abaf6d7614b874081159db7cc41e910bf47462
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Commit af02b05e59 ("mmc: add thunder boot support")
add this function wrong. So just remove it.
Fixes: af02b05e59 ("mmc: add thunder boot support")
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I9177c615163826e3df2ba692e63f9aadf48ef912
The power model node must be the child node of the device node.
Change-Id: Ib16e37c31e573f183ea304b072d2a7912e155197
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
to modify bus width error sometime plug out hdmi and switch cvbs output
Change-Id: Iaa7914fbccc99991fbfbc5495ba647f97997c8ba
Signed-off-by: Huicong Xu <xhc@rock-chips.com>
If HDMI output corlor mode is YCbCr422, the tmds clock is same
to YCbCr444 8bit, phy bus width should be set to 8.
Change-Id: I6e844e676a6315ae0cb88b0bd8456f0e27fa5e0c
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
1.Filling the HDMI AVI infoframe quantization range information.
2.If output is limited enable color space conversion to convert.
Change-Id: I75f666424f00f3f6ec695047f7851824e89cd1a5
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Under the following conditions, phy will be abnormally enabled.
1. HDMI is enabled in uboot.
2. disabled/bridge_is_on/phy.enabled/mc_clkdis were updated to
work when probe.
3. HDMI is disconnected.
4. drm_helper_probe_single_connector_modes update connector->status
to disconnected and power off phy by dw_hdmi_update_power. But the
polled type of HDMI is DRM_CONNECTOR_POLL_HPD, output_poll_execute
will not process this disconnection, and dw_hdmi_bridge_disable is
not called, hdmi->disabled is still false.
5. vop will be switch to Tv encoder, and dclk is 27MHz.
6. HDMI is connected.
7. dw_hdmi_update_power is called in dw_hdmi_irq, for hdmi->disabled
is false, then phy is powered up with parameter of 27MHz, and
bridge_is_on is set to on.
8. VOP switch to HDMI mode, set the new dclk rate.
9. dw_hdmi_bridge_enable is called, but the bridge_is_on is already on,
phy will not set again, still maintain the parameters that do not
conform to the new dclk rate.
This patch introduced an variable initialized to indicate hdmi is
initialized before probe, e.g. uboot. When power off hdmi, initialized
and disabled is updated.
Change-Id: I163967ac02e7f29ab586acbfd25d5a15679470c8
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Include the following commit:
1.update mc_clkdis in dw_hdmi_bind.
2.update more hdmi status in dw_hdmi_bind.
3.Fix hdmi can't display in android.
4.Update criteria to determine whether uboot logo is on.
5.disable phy in dw_hdmi_bind.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I4d1269062b0a4c01d0e82923bf9bb6dad3411387
Switch is no longer available in kernel 4.19, so
we use extcon instead.
the hdmi connect status node:
/sys/class/extcon/extconX/state
HDMI=0:
hdmi is disconnected
HDMI=1:
hdmi is connected
Change-Id: I806d8fd5b9b4b36f15aa6aec275fad2ecf122e91
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
