This patch doesn't fix any issue, but conforms
to linux coding style.
Change-Id: I87326a21594b905ea5791f73efc1cea0299abe4d
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Rk3399 support single and burst mode, and flushp instruction.
But burst mode improve transfer efficiency.
Please refer to:
Commit 8e770f371c
"dmaengine: pl330: add burst mode according to dts config"
Change-Id: I2eb36723697cf548dc75aca0e5a276a86cd2419d
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
set armclkb 816M to slove the crash,which reset core voltage below 0.85V.
So make sure the 0.8V voltage is enough for the init clk freq.
Change-Id: I4dba25fdfd610c0751f50ce09283c32a9b3f420f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Rockchip RK3399 SoCs support reboot with modes, such as recovery mode,
loader mode and normal mode.
Change-Id: I96ed872f849c2b3b06d236248995db18be070960
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Let's assign clk parent and rate for SCLK_EMMC to meet the
requiremen.
Change-Id: I3730a2124494da51717b1756f488f9df5bcd6423
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
We need to put the power status of HEVC IP into IDLE unless
we can't reset that IP or the SoC would crash down.
rockchip_pmu_idle_request(dev, true)---> enter idle
rockchip_pmu_idle_request(dev, false)---> exit idle
Change-Id: I76733efd2de4f7ee183c1b6bd1545d60038ee31b
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Randy Li <randy.li@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Before reboot if the DCDC is disabled,
the DCDC is still disabled after restart.
We have an method to workaround:
Use vsel pin to switch the voltage between value in FAN53555_VSEL0
and FAN53555_VSEL1. If VSEL pin is inactive, the voltage of DCDC
are controlled by FAN53555_VSEL0, when we pull vsel pin to active,
they would be controlled by FAN53555_VSEL1.
In this case, we can set FAN53555_VSEL1 to disable dcdc,
So we can make vsel pin to active to disable dcdc,
VSEL pin is inactive to enable DCDC.
Change-Id: I14c823ed11dc3369044ad2ed0b53a6027acbccd0
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
It has proved the controller has a potention broken state with a DTO
interrupt comes while the data payload is missing, which was not
covered by current software state machine. Add a xfer timer to work
around this buggy behaviour introduced by broken design.
Change-Id: I5019c5ba0cdeb59adcdd3a5231a2000b448762bc
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Android healthd try to listen power_supply subsystem uevent,
but which will block system from suspend on big.LITTLE system
because thermal_cooling_device_unregister will called when
cpufreq_exit. So ignore this uevent when suspend.
Change-Id: I35948498916560d5ec75fe561c9e9d588663ad22
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Add cru and pmucru regs dump when system panic.
It's just for debug.
Change-Id: I3f837f2941054129d20c2355d86f575d6ee84665
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
According to the advice of the IC,
setting the PMU_GPU_PWRDW/PWRUP_CNT regs 6 cycel(250ns) for RK3399 SOC.
Change-Id: I0449069a3b5035bd0442fcd74b645de9480a1d89
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
These clock rate are used for HDMI display.
Change-Id: I4742dcfe8ddedfa6b86c38ce03bcaa5c28b34c4e
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
When we use the MIPI screen, the driver will unprepare and disable
the phy_cfg, it will diable its parent pclk_vio:
dw_mipi_dsi_phy_init
--> clk_disable_unprepare
--> clk_disable
--> clk_core_disable(core->parent)
The pclk_vio supply power for pclk_vio_grf, hence, disable pclk_vio_grf will
cause other drivers failed to operate GRF.
Change-Id: I6d5bd27b9478da09209130f1fd5a62c0d4bb1785
Reported-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
We recommend, VOP0 is the main screen, VOP1 is a sub screen,
only VOP0 is able to re-set parent (VPLL) rate.
Change-Id: If40f95ce18e73477df8f7f031013333a603d5eb2
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Because frac div need to more than 20 multiple between the numerator
and denominator, but we need to be fit many HDMI/DP freqs and may
bring serious jitter when the dclk_vopx below the dclk_vopx_frac.
Therefore, we can select dclk_vopx below the dclk_vopx_div directly.
Change-Id: If3d9051211f0b160a507f0942667796f043f4ec2
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
We hope to be able to HDMI/DP can obtain better signal quality,
therefore, we move VOP pwm and aclk clocks to other PLLs, let
HDMI/DP phyclock can monopolize VPLL.
Change-Id: Ib715f9d29c0743d113f9f74886ff3921c9e0a327
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
We need to declare that we enable all NOCs which are critical clocks
always and clearly and explicitly show that we have enabled them at
clk_summary.
Change-Id: I859664692b4d1bb0dda0ee38295dfcbc3cc70019
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The reserved root blocks is not enough for booting Android due to
the limit of 0.2% if the fs size too small. so we add a new mini-
mum limit is 128MB.
Change-Id: I5af3b182001d27e4d18b4090c5270bbb2ac6253b
Signed-off-by: Cliff Chen <cliff.chen@rock-chips.com>
The f_blocks of statfs include file system overhead，it is not normal
usage of Posix.
Change-Id: If481626b08c05290626938586e2dc721690f1a91
Signed-off-by: Cliff Chen <cliff.chen@rock-chips.com>
If cmd is empty in get_reboot_mode_magic, we should return normal magic.
Change-Id: I10931adc49e33f72ae73d9471159f82cc02ff0c0
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
rk3288 ohci doesn't actually work on hardware, so we
need to disable it in ohci-platform driver.
Change-Id: I72750edda67358ff1e8fe66047bf60420500997e
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Like the runtime PM support patch of ohci-platform, we
add the same basic runtime PM for ehci-platform.
Conflicts:
drivers/usb/host/ehci-platform.c
Change-Id: I84cbb15dd393e6af69b4cf6887f1628e2cba4999
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Some EHCI controllers use usic phy (e.g rk3399/rk3288),
in order to enable these controllers, we need to set
some additional EHCI vendor-specific registers.
Support this feature in device tree when using the ehci
platform driver by adding a new property for it.
Conflicts:
drivers/usb/host/ehci-platform.c
Change-Id: I279ccfdb5866df49828825bfd41b39fcd58a2832
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
For the hardware bug of RK3288 OHCI, we use commit cfe6f1dd57
("usb: ehci: add rockchip relinquishing port quirk support") to fix
it previously. However, it have been ineffective after upstream commit
94c43b9897 ("USB: Check for dropped connection before switching to
full speed") was merged due to the condition of relinquishing port was
changed.
This patch adds an additional condition for the previous commit to ensure
no relinquish port quirk can take effect for RK3288 EHCI.
Change-Id: I0630265e101afb349816955e069e1c121745ac08
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
