Commit Graph

1059127 Commits

Author SHA1 Message Date
YouMin Chen
ff3405ff4c clk: rockchip: remove spin_lock in the rockchip_ddrclk_sip_set_rate
Change-Id: Ia3d04aef8fbf8093c2a3a89a845f948f69c8611f
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-07-26 19:04:41 +08:00
Finley Xiao
d2b92a90ea clk: rockchip: support setting ddr clock via SCPI and SIP Version 2 APIs
On rk3368, let a mcu scaling ddr clock via SCPI (System Control and
Power Interface) APIs.

Change-Id: I95342b876caad991e6d1319c5e4ec793365c7981
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
2021-07-26 19:01:46 +08:00
Steven Liu
c945c9dcda pwm: sysfs: Add PWM oneshot mode support
Allow a user to write pwm oneshot_count value. If oneshot_count == 0,
the pwm works in continuous mode. If 0 < oneshot_count < 256, the
pwm works in oneshot mode.

Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Change-Id: Icbcea85dc1d625a4ac24fee4ab07f1e2421bde77
2021-07-26 18:29:57 +08:00
Steven Liu
ea419b14d6 pwm: rockchip: Support pwm oneshot mode for specified number of cycles.
The oneshot_count value should be less than PWM_ONESHOT_COUNT_MAX.
If oneshot_count == 0, this pwm channel works in continuous mode.

Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Change-Id: I45857fb5762e0365cce5278502479c580638e40c
2021-07-26 18:29:57 +08:00
Tao Huang
c83c32522f video: rockchip: mpp: Fix compilation warning on ARM
In file included from drivers/video/rockchip/mpp/mpp_iommu.c:12:
./arch/arm/include/asm/dma-iommu.h:27:33: warning: declaration of
'struct bus_type' will not be visible outside of this function [-Wvisibility]
arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size);

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ieac6a2ab326a62fbb6831643519d55ab532ec3e9
2021-07-26 18:15:59 +08:00
Yu Qiaowei
865b1e840f video/rockchip/rga: Fix the error of dst R2Y color space abnormality.
This commit must be updated when using im2d api.

Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: I0cd8e53323f45c3410703f149587ea884cdbe624
2021-07-26 17:43:17 +08:00
Huibin Hong
5760581699 serial: 8250: support rx dma mode only
Most SOCS have only 8 or 6 channels, but have more than 16
peripherals. If those peripherals work together, some
fails to request dma channel, because there are no enough
channels. And maybe it's unnecessary to use dma for uart
tx. It is necessary for uart rx when hardware auto flow
control is not used.

&uart0 {
	dma-names = "!tx", "rx";  // disable uart tx with dma
	status = "okay";
};

Change-Id: Ia74477514ba57300a4d19a5c2565ae7b5b8ab521
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2021-07-26 14:31:51 +08:00
Huibin Hong
ec403a4036 serial: 8250_dma: support rockchip dma transfer
Change-Id: I0735c41c7d55770eb24c6dede62d623ae8285bdd
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2021-07-26 10:09:14 +08:00
Huibin Hong
fc7855d6f2 serial: 8250_dw: lost one byte sometime when receive
To avoid "too much work for irq" issue, cherry pick the patch.
It reads the RBR to clear the time out interrupt, but sometime the
rx fifo may be not empty while cpu reads the RBR. Which would cause
the data lost.

patch for "too much work":06451e93ab59e5b1843c29cbb468a274f4919563

By the way, current patch can't get rid of the risk entirely, so I
try a lot to solve it. Unfortunately, I only got the phenomenon that
lower pclk can reduce the probability. And I check the dw data sheet,
it has pclk and sclk, so there is synchronization problem. But it
only requires (slck < 4*pclk).

Change-Id: I01a36c689b43310294c45294abcf4982f5ddf2af
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2021-07-26 10:09:14 +08:00
Huibin Hong
b03cab30e2 serial: 8250_dw: clear time out interrupt when in dma mode
Change-Id: Iebeacce7cea7be8a71ae0dad17db5bcdeb26d52a
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2021-07-26 10:09:14 +08:00
Huibin Hong
b205560ab1 serial: 8250_dw: set uart clk according to baudrate
Change-Id: I27f92816b202bbe4fa9d97f7656721661afbaa6e
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2021-07-26 10:09:14 +08:00
Huibin Hong
62d96185bd serial: 8250_dw: uart wake up
Add wakeup-source to uart dts node to enable uart
wake up system when it receives data.

Change-Id: If4e82a4d3dbaca708209553dc3693089864c782f
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2021-07-26 10:09:14 +08:00
Steven Liu
bcdc525901 pwm: rockchip: Get pwm clk_rate in pwm_probe function
The clk_get_rate function is used in pwm_apply and pwm_config.
And it is not allowed in interrupt calls due to a mutex.
So move it into pwm_probe function.

Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Change-Id: I1766f282ccd1047e41f30cc55e3312fefe4b7388
2021-07-26 09:58:10 +08:00
Steven Liu
7711ebb8a5 pwm: rockchip: Add pwm output center aligned mdoe
Support pwm output aligned mode to switch from  left-aligned
to center-aligned. In dts, add "center-aligned".

Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Change-Id: I3e699c873a9ef533e59e11dbf9777001f205b4d9
2021-07-26 09:58:10 +08:00
Tao Huang
30d90a2d42 pwm: rockchip: Call rockchip_pwm_driver_init() early when CONFIG_ROCKCHIP_THUNDER_BOOT=y
Before pwm_regulator_driver_init().

Change-Id: Ia786e8baf54baf13dc9e56abd2e38a27b9cfb266
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2021-07-26 09:58:10 +08:00
David Wu
630556e0dd pwm: rockchip: Make pwm configure correctly for enable_conf
If some PWM enable_conf was configured with different values at
uboot/loader, the enable_conf should be cleaned firstly and
configured them at kernel. It is better to use the same parameters
on both sides to ensure excessive smoothing.

Change-Id: Ib1b7b55e9816639d9915543dadf059ce0e8be103
Signed-off-by: David Wu <david.wu@rock-chips.com>
2021-07-26 09:58:10 +08:00
David Wu
2d055eb091 pwm: rockchip: Disable irq for pwm config
Add irq disabled protection at the PWM configuration, which can
speed up the PWM configuration and reduce the possibility of
interrupting the configuration.

Change-Id: I8ca3c4b9790b747c12804fa82b51456a0de7fb92
Signed-off-by: David Wu <david.wu@rock-chips.com>
2021-07-26 09:58:10 +08:00
Sandy Huang
7c831dee39 pwm: rockchip: add pwm en for voppwm
voppwm is frame effect, so we need add vop pwm en to
indicate the pwm en state.

Change-Id: I1492322f99b638c8dc6cf03c87035f28dca3de8f
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
2021-07-26 09:58:10 +08:00
David Wu
91ae9813f5 pwm: rockchip: fix ioremap failed for voppwm
Change-Id: I3df7e2ee2b8cb24c4c8aad30cf6d55d11adf0573
Signed-off-by: David Wu <david.wu@rock-chips.com>
2021-07-26 09:58:10 +08:00
Mark Yao
5e4cf93c05 video: backlight: pwm_bl: fix backlight polarity
Backlight polarity not works without pwm_adjust_config.

Change-Id: I11e5eefe340f758b6721021f13238306b3721270
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
2021-07-26 09:57:01 +08:00
Shawn Lin
fece037fac mmc: sdhci-of-dwcmshc: Adjust DLL_TXCLK_TAPNUM_DEFAULT to 0x10
This value is better to be 0x10 instead of 0x16 by new test report
to keep all RK356x work consistently.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I87a22f6e02a6206981fe484db353613ac9a3ede6
2021-07-23 17:29:11 +08:00
Simon Xue
131703bbd9 video: rockchip: iep: fix build issue
1. fix iommu head file
2. fix slab head file
3. fix drm head file
4. drop api only work in kernel-3.10
5. fix iommu api

Change-Id: I551ceb4a01c4070dfbb5fa842a6790894177713e
Signed-off-by: Simon Xue <xxm@rock-chips.com>
2021-07-23 12:07:33 +08:00
Finley Xiao
ae3abb8c63 dt-bindings: power: add binding for rk3568 power domains
Add binding documentation for the power domains
found on Rockchip RK3568 SoCs.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I7544a643096948e75f59fb8126201b0de142440d
2021-07-23 11:41:35 +08:00
Finley Xiao
6e97bedf89 clk: rockchip: rv1126: Fix ispp parents' name
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I5bb9437320835a2a0cdb16c039aabd846bf1d682
2021-07-23 11:40:17 +08:00
Finley Xiao
6669a99505 clk: rockchip: rk3308: add cru regs dump for panic
Add cru regs dump when system panic. It's just for debug.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I3c39c974523238b0140492be5e9eceb1811b3945
2021-07-23 11:39:21 +08:00
Finley Xiao
ddbda6c6df clk: rockchip: rk3308: Set max parent rate of dclk_vop_frac for rk3308b
The max parent rate of dclk_vop_frac is improved to 800MHz on rk3308b.

Change-Id: Ie36120ac7048fc4c983547539a6bce34d737529d
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2021-07-23 11:39:21 +08:00
Sandy Huang
31307243fa drm/rockchip: analogix_dp: register analogix_dp to rockchip_drm_sub_dev_list
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Iae408b344ea17f1eaa3718b8f57fcd402de0a2d9
2021-07-23 11:36:15 +08:00
Sandy Huang
6cd7f48350 drm/rockchip: dsi: register mipi dsi to rockchip_drm_sub_dev_list
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I9dea09bb785344342875a9879b77edf8d8bb8639
2021-07-23 11:36:15 +08:00
Sandy Huang
e78097e89b drm/bridge: dw-mipi-dsi: add api to get connector
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Id024b178bf936f0af3a782fe2c54fde661cce0da
2021-07-23 11:36:15 +08:00
Yu Qiaowei
6d3cc78d0e video/rockchip: rga2: Fix MMU base not shift forward.
Since the MMU base is not shifted forward, when the sync/async mode
is called together, the same memory is used to store the page table,
resulting in data errors.

Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: If4807da8159e98a8d807cc24b4d6533793eeefa8
2021-07-23 11:19:18 +08:00
Algea Cao
c4bac4aa0b drm/rockchip: Add hdmi shutdown interface
When system shutdown, shutdown interface will be called.
Hdmi should be disabled when system shutdown.

Change-Id: I09ec1d7d3801bf8a8277c91072fa09bd1b430809
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2021-07-23 09:57:23 +08:00
Algea Cao
37fda45520 drm/bridge: dw_hdmi: initialize hdmi i2c when system resume
Change-Id: Ie9373517e255c91ded38a4e620d15d5cfd0bd9c4
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2021-07-23 09:57:23 +08:00
Algea Cao
495a7777d6 drm: bridge: dw-hdmi: set hdmi ddc pin HI-Z when suspend
Set hdmi ddc pin HI-Z to save power.

Change-Id: Ic5e15cac43c486e7de6be8526daea9b36da68bc8
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2021-07-23 09:57:23 +08:00
Huicong Xu
36549072d7 drm/rockchip: dw_hdmi: add power domain control
close pd when suspend, no when plug out because hotplug detect need it.

make hdmi probe before dp otherwise the shared power domain will be
close after dp probe and cause splash screen when starting kernel if
hdmi uboot logo display

Change-Id: I82ba1abdaf7567173df9ad900d57eca0e6be3932
Signed-off-by: Huicong Xu <xhc@rock-chips.com>
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2021-07-23 09:57:23 +08:00
Bin Yang
901d4890ec drm/bridge: dw_hdmi: clear ih_mute register when system resume
HDMI PD is power off when system suspend, so ih_mute register
bit0 mute_all_interrupt will be reset to 1 when system resume.
HPD interrupt will be mask, that would cause hdmi plugin could
not be detected.

Change-Id: I3bf2e6116e902cd516a7ac69fbe8569ca943e853
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2021-07-23 09:57:01 +08:00
Algea Cao
5d73d163ad drm: rockchip: dw-hdmi: Introduce HCLK_VOP for RK3566/RK3568
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ifcc15490b135692d955500114b59cbf8c326cacd
2021-07-23 09:50:08 +08:00
Algea Cao
3a99549ccd drm: rockchip: dw-hdmi: Add clk hclk_vio
Change-Id: If117c63f97c2af0811d29f322188ddc24470eadb
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2021-07-23 09:49:56 +08:00
Algea Cao
a22981924b drm: rockchip: dw-hdmi: Set hdmi output interface to HDMI0
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ia9c694f73c1fe9ae3bdb4d8774658dca566ef6c2
2021-07-23 09:49:49 +08:00
Shunqing Chen
31238b71f1 drm: rockchip: dw-hdmi: add RK3568 support
Change-Id: I24ec9a60d915b71281362b0b2d67fb8c288cdd14
Signed-off-by: Shunqing Chen <csq@rock-chips.com>
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2021-07-23 09:49:43 +08:00
Algea Cao
96afb6b92d drm: rockchip: dw-hdmi: Add encoder mode set
Update hdmi phy ref clock in encoder mode set.

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I8e1df8e3d9e4109e9beae5bdaaf82ea8cc070407
2021-07-23 09:49:34 +08:00
Shunqing Chen
25665e043a drm: rockchip: dw-hdmi: rename vpll_clk to accommodate more platforms
Change-Id: I6d5aaacc241add2bbd20f2e16f2b4ae798e1db6a
Signed-off-by: Shunqing Chen <csq@rock-chips.com>
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2021-07-23 09:49:19 +08:00
Mark Yao
5e564157e3 drm/rockchip: dw_hdmi: move vpll set rate to encoder enable
Change-Id: I5cf7f32f15cf1ea3e85b69009615756be3809c5e
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2021-07-23 09:49:08 +08:00
WeiYong Bi
a90aecefe5 drm/rockchip: dw_hdmi: Add support for rk3368
Change-Id: I6a49447a5edd53013ed81875f351089793914f77
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2021-07-23 09:48:57 +08:00
Tao Huang
b08c3f96b1 arm64: rockchip_gki.config: Enable sound codec modules
+CONFIG_SND_SOC_DUMMY_CODEC=m
+CONFIG_SND_SOC_ES7202=m
+CONFIG_SND_SOC_ES7210=m
+CONFIG_SND_SOC_ES7243E=m
+CONFIG_SND_SOC_ES8311=m
+CONFIG_SND_SOC_ES8396=m
+CONFIG_SND_SOC_RK817=m
+CONFIG_SND_SOC_RK_CODEC_DIGITAL=m
+CONFIG_SND_SOC_RT5640=m

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ifcc99079e59ea8cec692328aca483291a1a11568
2021-07-23 09:03:26 +08:00
Sugar Zhang
88b08f7ee7 ASoC: codecs: Add support for rockchip codec digital interface
This patch adds support for rockchip codec digital interface,
which is used to communicate with external codec analog part
with pdm link.

Change-Id: I9ea7020d904b63f7a34696b0f538accd8c700076
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2021-07-23 08:45:41 +08:00
Binyuan Lan
970d35ba6b ASoC: es7210: add es7210 I2S adc support
ES7210 is a 4-ch ADC with I2S interface for Microphone Array

Replace digital_mute with mute_stream

Change-Id: I71faf344eb8b058349a7a889eae296115cc788c8
Signed-off-by: Binyuan Lan <lby@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2021-07-22 20:44:46 +08:00
Binyuan Lan
70a8170ba5 ASoC: es7243e: add es7243e I2S adc support
ES7243E is 2-ch ADC with I2S interface for Microphone Array

Replace digital_mute with mute_stream

Change-Id: I3c61f5feccad9362e2859d7646e88a0e990c998c
Signed-off-by: Binyuan Lan <lby@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2021-07-22 20:42:49 +08:00
Binyuan Lan
1e7cbe5fb7 ASoC: es7202: add es7202 pdm adc support
ES7202 is 2-ch ADC with PDM interface

Replace digital_mute with mute_stream

Change-Id: Id204f592ed91bbdddd71b6dda2e6e0bbae4bb9e8
Signed-off-by: Binyuan Lan <lby@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2021-07-22 20:40:10 +08:00
Xing Zheng
a72f5c27d0 ASoC: es8311: add support es8311 codec driver
Replace digital_mute with mute_stream

Change-Id: Iae35145535664754f3babf4245c9682077c1fc00
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2021-07-22 20:30:08 +08:00
Xing Zheng
ff74b915f2 ASoC: wm8974: add support enable/disable external mclk on runtime
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Change-Id: I6711bf6ca1406036eafe3755e9595414bfedcb3f
2021-07-22 20:29:37 +08:00