For rk3576, pwm1 supports wave generator mode, which
relies on the osc clk.
Change-Id: Icac6a8201aa0370868e0383f2b9daa90919cea9e
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
For rk3506, pwm0 supports wave generator mode, which
relies on the osc clk.
Change-Id: I8897595eeda31b0f606c2f2f6a365a1125fceeac
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The read/write behavior of wave table relies on the osc clk
by default.
In addition, replace pwmchip_add() by devm_pwmchip_add().
Change-Id: Idfae114cf51e30c4c82ed5255477eef8d969aa2e
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
This reverts commit e1f0e15a08.
rk3588 use ahci_dwc driver other than ahci_platform.
Change-Id: Iaefe35363ded3730d978ef330ae9a08b872f4379
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Commit 33629d3509 ("ata: ahci: Add DWC AHCI SATA controller support")
move snps,dwc-ahci support from ahci_platform.c to ahci_dwc.c.
So replace CONFIG_SATA_AHCI_PLATFORM by CONFIG_AHCI_DWC.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I4089d656f93fedd8d9437ebb1d2ed5431915b8df
Reading uboot phy status must before phy pll clk register,
otherwise phy pll will be enabled and set defualt 74.25Mhz rate.
Change-Id: I569499e0c3522f7f80f4aa0ff6cdda6a357d7fef
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
same as link mode, add spinlock for ccu mode
Change-Id: Ic6abe20edd6d932a25b832566504f8372002f897
Signed-off-by: Chandler Chen <chandler.chen@rock-chips.com>
For RK3399, the lcdc_sel should be set to corresponding id
for vopl or vopb.
Fixes: d4f217f532 ("drm/rockchip: analogix_dp: fix the log to indicate edp data source")
Change-Id: I98f5f50b32038025fe72a6d38e37fb02b011eaba
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Since CLK Master/Slave had been changed to Provider/Consumer
on kernel-6.1 or later.
So, do the same change for multi-dais driver to work well.
Nothing changed if property omitted in DT.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I439cb076cc35d06cbe0834f2169c6b30348f5775
before:
text data bss dec hex filename
4831493 2082556 107336 7021385 6b2349 vmlinux
after:
text data bss dec hex filename
4875062 2110588 106440 7092090 6c377a vmlinux
Change-Id: Ie82c5701049337a79dd80bfbea68de87df9fab7e
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
FLEXBUS_TX_WIDTH conflicts with the register name. Rename
FLEXBUS_TX_WIDTH to FLEXBUS_TX_WIDTH_4
Change-Id: I1a8cd1c9f7db22cb5f3c35e1479bae37c0bf5284
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Update win dly number according new TRM. Without this commit, the left 4
columns will display black when act width is 2048.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ie8b6d999c530c8836cb847e8809c5cdc6a3fdc7b
The ADC_IP bit controls all powers of the codec.
Change-Id: Iaaa4f277093023e430b98e9f1d343d3f0e5086ba
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Pulling down the phy reset pin can directly reduce the
power consumption of the phy.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I04355593fc2867fcf5f48543b6c4d0fb8b8ab159
CONFIG_ROCKCHIP_MINI_KERNEL enabled in some project which perform DMA
into kmalloc area that may cause data corrupt. Use a independent config
CONFIG_ROCKCHIP_KMALLOC_NO_USE_ARCH_DMA_MINALIGN instead of CONFIG_ROCKCHIP_MINI_KERNEL
Fixes: c97fea6ed1 ("slab: allows kmalloc min size independent on arch dma min alignment when CONFIG_ROCKCHIP_MINI_KERNEL=y")
Change-Id: Idd36490d695a0f2910d2b453228688405efdd43a
Signed-off-by: Simon Xue <xxm@rock-chips.com>
When system wakeup, It will call _dwc2_hcd_resume function and the
port_suspend_change flag will be set to 1 in _dwc2_hcd_resume function.
But in current code, the autosuspend delay for hub is set to zero and
this will cause a strange phenomenon where the USB bus will repeatedly
suspending and resuming.
Considering that setting the port_suspend_change to 1 is only applicable
for partial power mode, there is no need to set port_suspend_change to
1 when DWC2 IP not support partial power mode.
Fixes: c74c26f6e3 ("usb: dwc2: Fix partial power down exiting by
system resume")
Change-Id: Ia57bfb8502cb55a5d9375a5ad609ac4104ff8acb
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
This patch fix the port cannot suspend when a HUB is connected. The
DWC2 IP on Rockchip SOCs does not support clock gating and Current
code places the port suspend within the dwc2_host_enter_clock_gating
function, which results in the port being unable to suspend.
Change-Id: I40fe73d116a30fec6c01a8c3c988653a48175f7f
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Current Code USB2 PHY use extcon notifier to send USB charger
types to power driver. If we use gpio to detect vbus or id state,
the extcon device is allocated and registered by extcon-usb-gpio.c
driver and USB2 PHY obtains this extcon device through DTS. If
these cables are missing, it will cause USB2 PHY driver to be
unable to set the status of these cables, leading to functional
abnormalities.
Change-Id: Iec27dfde4ec8bf12294bd6c57c3db5dada2f35cd
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Disable vcc if it exists, so the rom code could relink the device
from the init state.
Change-Id: I4493df466f3ea60b8c7a7e3befd110311fce6f6c
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
The Linux OS uses the device tree to detect the wifibt module,
particularly the Bluetooth module's UART, identified via
`/sys/firmware/devicetree/base/pinctrl/wireless-bluetooth`.
Some RK3566/RK3568 board configurations redundantly register the pinctrl
for wireless-bluetooth, causing script failures in UART identification.
This commit removes the redundant node to resolve conflicts and ensure
correct UART identification for Bluetooth communication.
Change-Id: Id55c48bda38275c04a365b0ede1f740baf767da2
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
BACKGROUND
A short clk giltch (~200us) found on the mclk calibrate case in
kernel 5.10.
mclk-12.288M - mclk-49.152M (~200us) - mclk-12.288M
The root cause is:
clk_set_rate(mclk_parent, 49.152M)
clk_set_rate(mclk, 12.288M)
Prefer to get the mclk rate div from mclk_parent rate, Unfortunately,
the latter will change the mclk_parent rate again in kernel 5.10.
So, do not change mclk parent's rate when it is multiple mclk already,
let clk framework handle it.
e.g.
mclk: clk_i2s1_8ch_tx mclk_parent: clk_i2s_8ch_tx_src
clk_i2s1_8ch_tx_src 0 0 0 12288000
clk_i2s1_8ch_tx_mux 0 0 0 12288000
clk_i2s1_8ch_rx 0 0 0 12288000
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ie9e869a48b65e287e60545626e92c9090ab02229
API snd_soc_register_component will try to rebind card per
each component register. and the ASoC allow no-pcm card instance.
devm_snd_soc_register_component
snd_soc_try_rebind_card
snd_soc_bind_card
snd_soc_add_pcm_runtime
devm_snd_dmaengine_pcm_register
So, we should register PCM before DAI component.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I275e919495280568b6b732097532f466a0cc3a2a
API snd_soc_register_component will try to rebind card per
each component register. and the ASoC allow no-pcm card instance.
devm_snd_soc_register_component
snd_soc_try_rebind_card
snd_soc_bind_card
snd_soc_add_pcm_runtime
devm_snd_dmaengine_pcm_register
So, we should register PCM before DAI component.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I8de05cf709187afd406775998f58ed5ebdb39d38
