Fixes: f9e002e86f ("drm/rockchip: dw-dp: Add full output bus format support")
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ib644ce28a5963082989e5345f046aca591c63166
This patch aims to tuning the high speed Tx signal for
4 independent USB2.0 PHYs of RK3588.
1. Adjust the HS DC level voltage from design default
4'b0110:0 to 4'b1001:+5.89%.
2. Adjust the HS Transmitter pre-emphasis current control
from design default 2'b00 disabled pre-emphasis to
2'b10 2x pre-emphasis current.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: If212a606113fd4409d9a33a25a04f8416336f6e4
The default aux tx amplitude level can't satisfied some
device, which will cause the aux communication failed.
Enhance the aux tx amplitude to a high level to be
compatible with different devices.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Idcb5cf2fcf91dda5985744acb4ad3e62c99ffba4
The dus clk shouled be enabled before restore qos.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ic981fc6d680a9be4c441c946715bf709c4e83e7b
The rkvdec2 link mode irq print should print both link status and core
status.
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
Change-Id: I2fffc0935260e6f3dcb788dffc1a467e6be5a7cb
The drm core will disable than enable a crtc when is marked as
connectors_changed.
But when we attach a writeback connector to a running
crtc, we really don't need this disable/enable, which
will black a running screen.
Change-Id: I636615f27424bc60496ffc487c218f60fb95d719
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Calling it from rockchip_p3phy_rk3588_init() will cause a timing
problem that PCIe3 enum and PCIe2 accessing combophy at the same
time which would cause problems. Changing PHY mux and enum devices
at the same time doesn't meet design purpose. So we also need to
move phy mode settings to probe as what comphy driver did.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I8689ed52db002a6eb0429bf528e2303fbf3cc449
value[3] is the value need to set, but the offset is value[1]
or value[2]. We need offset here.
Fixes: e984bc2a96 ("phy: rockchip: naneng-combphy: Add config option for pcie1ln-sel")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Ia5fca2bd4563e9618c52d601a47a28dc44fb48cc
This reverts commit 33d95b67b3.
As the probe of PCIe controller is threaded. So rockchip_combphy_pcie_init
may change PHY mux settings just between another controller's
signal accessing PHY. This doesn't meet design purpose. We should
keep mux settings ready before everything starts.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Iba59bd39741b97442b5f7fe91314aea3f1d0c533
V2:
key: remove Non existent key
panel: use simple-panel driver
regulator: correct usb gpio
gpio: add hub_en,camera_en
fix some typo
V3:
WIFI/BT: add support
V4:
remove Makefile for easy rebase
V5:
fixed wifi_pwren issue
support pcie ssd
increase Sdio Driver Strength Selection
V6:
support es8326/es7243e/pdm sound
Supports DP dual display
fixed PINCtrl conflict
V7:
support sc8886
disabled pcie now for some board can not boot
Add the hardware mouse layer
V8:
support cw2017
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Change-Id: Ia516536751ac645b704b5cae9bb275bd48b5aba8
Call phy_power_off and phy_exit if failed, so phy will
be reset and gated.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: If82b86704317e3a27217ab0c6a827af30463e7ba
SPLL has been set in SPL and UBOOT.
Kernel resetting causes mipi display jitter.
Note: If without Uboot, SPLL needs to be set in advance.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I59475ce1ea7712069e6c4a445a432d77f19227d5
The default autosuspend delay of runtime pm is 5000ms,
it's too long for the application scenario of hot plug.
If usb plug out and plug in again in 5000ms, it will
fail to do runtime suspend/resume, and also fail to
do usb phy ops. For RK3588 Type-C USB3.1 Gen1, it needs
to do usb3 phy init for normal or flip orientation
during dwc3 runtime process. This patch sets the runtime
autosuspend delay to 100ms for user's normal hotplug
operation.
Given the autosuspend delay 100ms is very short, it may
cause the usb device role fail to connect to usb host
in the following case:
1. Use Type-C to Type-A cable, connenct RK3588 usb to PC.
2. The TCPM set the usb role as PERIPHERAL and call
dwc3_usb_role_switch_set() -> __dwc3_set_mode() ->
dwc3_runtime_resume() -> power on u2/u3 phy ->
delay 100ms -> dwc3_runtime_suspend().
3. In the dwc3_runtime_suspend(), it will check the
dwc->connected which can only be set to true in the
dwc3_gadget_reset_interrupt().
4. If the PC usb host doesn't send reset signal within
100ms, the dwc3 will do dwc3_runtime_suspend() and
power off u2/u3 phy. This cause usb device not to
be detected.
So this patch fix the runtime pm mechanism for usb device
role to forbid dwc3 enter runtime suspend if the desired
role is PERIPHERAL. And allow dwc3 to enter runtime suspend
again after the desired role is not PERIPHERAL. For the usb
host role, the xHCI platform driver has forbidden it to
do autosuspend, so we don't care the usb host role here.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I195a5fd7d8264108dd32f56f5b9bdb7f0e83da90
Some times we want change a overlay plane defined in vop2_reg
to primary plane.
Change-Id: I5f563fb258a66278255be762ebdfca21b51aabd1
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Set the dr_mode to peripheral for rk3588-evb2 and
rk3588s-evb2 which can't support usb mode detection
automatically for the time being.
In the near future, we will support usb device/host
mode switch by software, then we can revert this patch.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I618b7e32eabb2b4106f0f844125fca5c85ce33c8
1. Set the dr_mode to otg for rk3588-evb and rk3588s-evb;
2. Remove the maximum-speed hs limit for rk3588s-evb;
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Ia6ab7e259207fc33c2e38bd8ae4864f06b4bf3d8
after this commit, axi id is used as the following rules:
AXI0
Cluster0:
win0: 0x2，0x3
win1: 0x4，0x5
Cluster1:
win0: 0x6，0x7
win1: 0x8，0x9
Esmart0: 0xa, 0xb
Esmart1: 0xc, 0xd
Lut: 0xe[for vp0/2, will be used at different time]
AXI1:
Cluter2:
win0: 0x2，0x3
win1: 0x4，0x5
Cluster3:
win0: 0x6，0x7
win1: 0x8，0x9
Esmart2: 0xa，0xb
Esmart3: 0xc, 0xd
Lut: 0x1[for vp1]
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Iae865835e49ba8ca0197b0f015d7709cba23e8b3
Organize the code, separate rga_job_assign to rga_policy.c
Signed-off-by: Li Huang <putin.li@rock-chips.com>
Change-Id: Ie84cd14db23fba35db2da7c77edecb5b5bcc621b
