Enable isp will cause system to halt on android booting, which
is caused by wrong voltage for vdd_gpu.
isp will set gpio directly, unfortunatly, it sets the enable gpio
of dc-dc for gpu.
There has no good solution for isp to fix this issue, so let's
disable the isp node for rk3399 evb3 firstly to make board works
well.
Change-Id: I5dd8c367a192ce793ed388aaf143125550e90621
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
The AUO B125HAN03.1 panel is a 12.5' FHD 16:9 Color TFT-LCD
and 30 pins eDP interface.
Change-Id: Ic2be5f1d5a3e25d805e0752c1c1fad0decc4f2d0
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
The BOE NV125FHM-N73 panel is a 12.5' FHD 16:9 Color TFT-LCD
and 30 pins eDP interface.
Change-Id: Idc15fb7126bf778fd23a766b01c2d5cf9760d4f3
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
Reset isp mmu would failed when attach,just ignore reset operation
Change-Id: Ib323db151e7313635524526d5304e16b9b504201
Signed-off-by: Simon <xxm@rock-chips.com>
Use win->offset for window ext config is wrong,
cause yuv color space display abnormal.
Change-Id: I425c412767ad1014cff0707e549d17534fa8059b
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Add devicetree bindings for Rockchip grf which found on
Rockchip SoCs.
Change-Id: Iac0913b71925f7ddc0edd10b34024b049aace964
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit fe95effb4c)
The patch fixes the warring when rk3399-vr resume:
CPU4: found redistributor 100 region 0:0x00000000fef80000
CPU4: update cpu_capacity 1024
CPU4: Booted secondary processor [410fd082]
rk3x-i2c ff3c0000.i2c: timeout, ipd: 0x10, state: 1
rk3x-i2c ff3c0000.i2c: timeout, ipd: 0x10, state: 1
rk3x-i2c ff3c0000.i2c: timeout, ipd: 0x10, state: 1
cpu cpu4: _set_opp_voltage:
failed to set voltage (800000 800000 800000 mV): -110
cpu cpu4: failed to set volt 800000
CPU4 is up
Detected PIPT I-cache on CPU5
CPU5: found redistributor 101 region 0:0x00000000fefa0000
CPU5: update cpu_capacity 1024
CPU5: Booted secondary processor [410fd082]
CPU5 is up
Change-Id: I36f1b5d23c8d2436e20765d699dfde9eb8cf74fa
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Add the clock tree definition for the new rk3328 SoC.
Fix up the pll setting to support rk3328 SoC.
Change-Id: Icf887625697515cf3e2cd2f7da7956a57c7e558a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add the dt-bindings header for the rk3328, that gets shared between
the clock controller and the clock references in the dts.
Add softreset ID for rk3328.
Change-Id: I8e6301fd854fe5c9a820fe76d7826db2c1c08b4e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
camera will query this property, this is historical issue!!!
Change-Id: Ida221e9f5781dcc5562cad69e2ac437290b946bb
Signed-off-by: Jung Zhao <jung.zhao@rock-chips.com>
Add an ethernet0 alias for the RK3288 mac interface so
that u-boot can find the device-node and fill in the mac address on
boards that support a wired network interface.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: Ie8c4e0d90b62278485446f614fce0c95145432d9
(cherry picked from commit 85ef8d611f)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
In order to use Wake-on-Lan on RK3288 integrated MAC, we need to wake-up
the CPU on the PMT interrupt when the MAC and the PHY are in low power mode.
Adding the interrupt declaration.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Change-Id: Iec2637cc0448b6d93b895ca8f4176bab0a1f2dfb
(cherry picked from commit d5bfbeb809)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
The mipi controller node does contain an unused reg property as well as
unnecessary #address-cells and #size-cells properties for subnodes
not using addresses, so remove those to also make dtc happy.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>
Change-Id: I48166c93f7746fa88fe2b35c3a040048926cadf7
(cherry picked from commit 6b241fcccb)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
The MIPI controllers are part of the VIO power domain so add the
necessary property to indicate this for the controller we support.
Signed-off-by: John Keeping <john@metanate.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I1d51ba1b91dcacb4dfbd6a23d3e609cb66b9426e
(cherry picked from commit 1946a201b3)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
In order to be standard to manage for rockchip SoCs, move the thermal
data into rk3288 dtsi, we needn't to add a new file for thermal.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: Eduardo Valentin <edubezval@gmail.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I2b11b46d1cfb9b70882d1062dedc5b8ff1bd5adf
(cherry picked from commit f87305fa00)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
The power-domain sub-nodes do have reg properties, but so far are
missing the expected unit names. So add the missing ones.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>
Change-Id: I03d82afdc2f170c7ecce9685e15b418ca5d30d5a
(cherry picked from commit 95cface95b)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
The usbphy subnodes do have a reg property but no unitname, add them.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>
Change-Id: I5b48e289b332397ab7c383b839b875aeefa9f114
(cherry picked from commit a8f0fa2764)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
The usb-phy is fully enclosed in the general register files (GRF).
Therefore as seen from the device-tree it shouldn't be a separate
platform-device but instead a sub-device of the GRF - using the
simply-mfd mechanism.
As the usb-phy is part of the kernel for some releases now, we keep
the old (and now deprecated) binding for compatibility purposes.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Change-Id: I747a18fba361d6c6f161b6572e43955e18593a34
(cherry picked from commit a0da445aab)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
The displayport-phy is fully enclosed in the general register files (GRF).
Therefore as seen from the device-tree it shouldn't be a separate platform-
device but instead a sub-device of the GRF - using the simply-mfd mechanism.
The driver entered the kernel in the current merge-window, so we can still
adapt the binding without needing a fallback, as the binding hasn't been
released with a full kernel yet.
While the edp phy is fully part of the GRF, it doesn't have any separate
register set there, so doesn't get any register-area assigned.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Change-Id: I44a857051be195386fc888b2c713bedc948d5c95
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(cherry picked from commit 0311c76e47)
IO-domain handling is part of the general register files, so should live
under the grf directly. This change allows the grf to be a simple-mfd and
the io-domains fetching the syscon regmap from that parent-node.
The old binding is of course preserved, though deprecated.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Change-Id: I562e293fc96283edc868771851f15dba0e80d3bc
(cherry picked from commit bc19b9a81d)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
The rk3288 usbphy is completely enclosed in the general register files
and the updated binding allows it to be a subnode of the GRF now.
So move the node appropriately.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I85ca27786da0cd388ef6b4fddb11747761a579a3
(cherry picked from commit 546a3521f2)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
io-voltage control is actually part of the grf, so move the node under the
newly available grf simple-mfd.
To minimize duplicate code, the core node and compatible property
gets placed in the core rk3288.dtsi while the individual boards
now only need to enable it and add the necessary supply properties.
cherry picked from commit 4b91545072)
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Conflicts:
arch/arm/boot/dts/rk3288-miqi.dts
arch/arm/boot/dts/rk3288-rock2-som.dtsi
Change-Id: I4f5ecc16524c52e8ac6f04cf8b9cdc0e1b7d937f
(cherry picked from commit 3445b2fae5)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
The edp-phy control is a part of the General Register Files and
with a recent patch in 4.6 the phy driver can now also handle this
correctly, so move the dts node under the GRF as well.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I6be6270739520f758dbe388cdbd50896c1d7d6f1
(cherry picked from commit 4b91545072)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Similar to the pmu, the general register files contain a lot of different
setting bits grouped into general registers, but also some somewhat special
entities like the controls for some phy-blocks or the io-voltage control.
To be able to move these blocks under the grf node where they actually
belong, make it a simple-mfd.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I2c7f9d6f4411ea05520515a45acbaa689814c872
(cherry picked from commit 6e38e6b26e)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Now vpu driver support both drm and ion allocator. And have
test on rk3399-mid(drm android 7.1), rk3399-mid(ion android
6.0), rk3288(linux mini arm) platform.
Change-Id: I0096c3928849b1f11a62378675f4559b4f101445
Signed-off-by: Jung Zhao <jung.zhao@rock-chips.com>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Randy Li <randy.li@rock-chips.com>
The return value of iommu_map_sg is size_t, it's unsigned
Change-Id: Ib06f61c020510673bc513e1a8fde6fd3980a7ca3
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Since (cacb6f5 FROMLIST: drm/rockchip: Use common IOMMU API to attach
devices), rockchip drm use common IOMMU API, the boot logo buffer
mapping need change to new api.
Change-Id: Ifa2c886e05d2de65de53a868458c56859519a0f2
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Some bootloader will check the reboot mode to take different action, so
we treat unrecognized reboot mode as normal mode to prevent the system
run into abnormal case.
Change-Id: I88063a5b41e4e645443229fa490b2b55db5ccf27
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
in drm mode ion is not support dma fd, in order
to support drm fd rga driver need fix, and user
also need set the buf type by the macro
Change-Id: I3d0eaf7fbefda5aaf715772649d972b9a9d5c06d
Signed-off-by: Zikim,Wei <wzq@rock-chips.com>
In current code, the connect status will be set to connected state when
reset interrupt occur and change to disconnected state in disconnect
interrupt.
But the usb charger may bring about reset signal in accident if we
connect and disconnect quickly. In this case, the dwc3 controller will
change link state and set to connect status, yet not change to
disconnected state when disconnect. So the dwc3 controller suspend
fail and result in a mistake when quick reconnect.
This patch set connect status to connected state when transfer complete
to make sure that usb is connect to PC exactly.
Change-Id: I8e5894d2e08b88bb5434222100d8f5c91c9f1a9d
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
DWC3 controller still need to read or write memory after dwc3
rockchip receive disconnect notify, the dwc3 controller will not
suspend immediately and the clock is still enabled even if we put
dwc_rockchip sync. So if we reconnect to PC quickly, the transer
will start before dwc3 rockchip receive connect notify and the dwc3
controller will reset during normal transer which result in the gadget
function break.
In order to suspend dwc3 controller and disable clock when transfer
finish immediately, this patch wait for usage_count of dwc3 controller
change to 1 and disconnect interrupt occur then suspend dwc3 controller
and disable clock, make the dwc3 continue transfer after dwc3 rockchip
receive connect notify, otherwise do not reset and get or put dwc3
controller if timeout.
Change-Id: If65344557d77370e9b6cf4bfea84175c37f00057
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Floating charger is a kind of special USB charger that
dp/dm not shorted, which is incompatible with BC1.2 spec.
However, we need to support this floating charger, and
consider that the max charge current of floating charger
is the same as standard USB charger (dp/dm is shorted),
so we set the charger type as DCP for floating charger.
Change-Id: Ifaca7269a3d4660ac095c59776d7e935fe6126df
Signed-off-by: William Wu <wulf@rock-chips.com>
