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Thirumalesha Narasimhappa
408217c2f7 UPSTREAM: mtd: spinand: micron: Add support for MT29F2G01AAAED 
The MT29F2G01AAAED is a single die, 2Gb Micron SPI NAND Flash with 4-bit
ECC

Change-Id: I6b1baaef7e092bf932a8fdbcb66d3db2e36ef900
Signed-off-by: Thirumalesha Narasimhappa <nthirumalesha7@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20201108113735.2533-3-nthirumalesha7@gmail.com
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 8c573d9419)
 2021-09-16 10:35:44 +08:00
Thirumalesha Narasimhappa
f9df464e4c UPSTREAM: mtd: spinand: micron: Use more specific names 
Rename the read/write/update of SPINAND_OP_VARIANTS() to more
specialized names.

Change-Id: I5c02b9bf76376ea4ed320cf49be1f7630329dfc3
Signed-off-by: Thirumalesha Narasimhappa <nthirumalesha7@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20201108113735.2533-2-nthirumalesha7@gmail.com
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit bdb84a22b0)
 2021-09-16 09:50:33 +08:00
Miquel Raynal
91915f631e UPSTREAM: mtd: spinand: Fill a default ECC provider/algorithm 
The SPI-NAND layer default is on-die ECC because until now it was the
only one supported. New SPI-NAND chip flavors might use something else
as ECC engine provider but this will always be the default if the user
does not choose explicitly something else.

Change-Id: Ia437dda2d2a43007bf04e2e6a072610c283c97d6
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200930154109.3922-6-miquel.raynal@bootlin.com
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit c8efe01028)
 2021-09-16 09:36:51 +08:00
Miquel Raynal
a516594d0c UPSTREAM: mtd: spinand: Instantiate a SPI-NAND on-die ECC engine 
Make use of the existing functions taken from the SPI-NAND core to
instantiate an on-die ECC engine specific to the SPI-NAND core. The
next step will be to tweak the core to use this object instead of
calling the helpers directly.

Change-Id: I91c0f9cd7da6f805fdd21b1a014c3446c6fa8813
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200930154109.3922-4-miquel.raynal@bootlin.com
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 945845b54c)
 2021-09-16 09:35:17 +08:00
Miquel Raynal
4ac6f9b33e UPSTREAM: mtd: spinand: Move ECC related definitions earlier in the driver 
Prepare the creation of a SPI-NAND on-die ECC engine by gathering the
ECC-related code earlier enough in the core to avoid the need for
forward declarations.

The next step is to actually create that engine by implementing the
generic ECC interface.

Change-Id: I1730a95750b49f2f6653bbf8db81478e7819f4c6
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200930154109.3922-3-miquel.raynal@bootlin.com
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 55a1a71a7f)
 2021-09-16 09:34:40 +08:00
Jaime Liao
be50629ec0 UPSTREAM: mtd: spinand: macronix: Add support for serial NAND flash 
Macronix NAND Flash devices are available in different configurations
and densities.

MX"35" means SPI NAND
MX35"LF"/"UF" , LF means 3V and UF meands 1.8V
MX35LF"2G" , 2G means 2Gbits
MX35LF2G"E4"/"24"/"14",
E4 means internal ECC and Quad I/O(x4)
24 means 8-bit ecc requirement and Quad I/O(x4)
14 means 4-bit ecc requirement and Quad I/O(x4)

MX35LF2G14AC is 3V 2Gbit serial NAND flash device
(without on-die ECC)
https://www.mxic.com.tw/Lists/Datasheet/Attachments/7926/MX35LF2G14AC,%203V,%202Gb,%20v1.1.pdf

MX35UF4G24AD is 1.8V 4Gbit serial NAND flash device
(without on-die ECC)
https://www.mxic.com.tw/Lists/Datasheet/Attachments/7980/MX35UF4G24AD,%201.8V,%204Gb,%20v0.00.pdf

MX35UF4GE4AD/MX35UF2GE4AD are 1.8V 4G/2Gbit serial
NAND flash device with 8-bit on-die ECC
https://www.mxic.com.tw/Lists/Datasheet/Attachments/7983/MX35UF4GE4AD,%201.8V,%204Gb,%20v0.00.pdf

MX35UF2GE4AC/MX35UF1GE4AC are 1.8V 2G/1Gbit serial
NAND flash device with 8-bit on-die ECC
https://www.mxic.com.tw/Lists/Datasheet/Attachments/7974/MX35UF2GE4AC,%201.8V,%202Gb,%20v1.0.pdf

MX35UF2G14AC/MX35UF1G14AC are 1.8V 2G/1Gbit serial
NAND flash device (without on-die ECC)
https://www.mxic.com.tw/Lists/Datasheet/Attachments/7931/MX35UF2G14AC,%201.8V,%202Gb,%20v1.1.pdf

Validated via normal(default) and QUAD mode by read, erase, read back,
on Xilinx Zynq PicoZed FPGA board which included Macronix
SPI Host(drivers/spi/spi-mxic.c).

Change-Id: I9f5e6cd3aee2f8951c8f16e1d1c24c13f13511fc
Signed-off-by: Jaime Liao <jaimeliao@mxic.com.tw>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/1621475108-22523-1-git-send-email-jaimeliao@mxic.com.tw
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit c374839f9b)
 2021-09-16 09:32:26 +08:00
YouChing Lin
72b926e26f UPSTREAM: mtd: spinand: macronix: Add support for MX35LFxG24AD 
The Macronix MX35LF1G24AD(/2G24AD/4G24AD) are 3V, 1G/2G/4Gbit serial
SLC NAND flash device (without on-die ECC).

Validated by read, erase, read back, write, read back on Xilinx Zynq
PicoZed FPGA board which included Macronix SPI Host(drivers/spi/spi-mxic.c)
& S/W BCH ecc(drivers/mtd/nand/ecc-sw-bch.c) with bug fixing patch
(mtd: nand: ecc-bch: Fix the size of calc_buf/code_buf of the BCH).

Change-Id: I88c68306bdc61a856cef9e5af1bc4c1e19fc2abd
Signed-off-by: YouChing Lin <ycllin@mxic.com.tw>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/1607570529-22341-3-git-send-email-ycllin@mxic.com.tw
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit ee4e0eafa4)
 2021-09-16 09:31:59 +08:00
YouChing Lin
57aaaa225f UPSTREAM: mtd: spinand: macronix: Add support for MX35LFxGE4AD 
The Macronix MX35LF2GE4AD / MX35LF4GE4AD are 3V, 2G / 4Gbit serial
SLC NAND flash device (with on-die ECC).

Validated by read, erase, read back, write, read back and nandtest
on Xilinx Zynq PicoZed FPGA board which included Macronix SPI Host
(drivers/spi/spi-mxic.c).

Change-Id: I1603b4acd8c62720de245d70543b4743deaa7ad5
Signed-off-by: YouChing Lin <ycllin@mxic.com.tw>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/1604561020-13499-1-git-send-email-ycllin@mxic.com.tw
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 5ece78de88)
 2021-09-16 09:31:59 +08:00
Jon Lin
76e07d846c drivers: rkflash: support gc 
Run a thread for nand gc.

Change-Id: I093fce2db9f511eda2d17e276ff3b350051f4b9e
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2021-09-16 09:21:35 +08:00
Wyon Bi
50d652bdf7 drm/bridge: analogix_dp: Fix display corruption in low temperature environment 
Change-Id: I46b3dbc57c1f2b8482559d4ba44bd7f339657ccd
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2021-09-15 16:19:22 +08:00
Liang Chen
9c4bb7cf64 mmc: dw_mmc-rockchip: set default pm_runtime status to active 
pm_runtime_force_suspend/pm_runtime_force_resume will not work
if the device is in suspend when pm_runtime is disabled.

Change-Id: I7179ecab2b059b43fab6d84683e52ae5c21096ae
Signed-off-by: Liang Chen <cl@rock-chips.com>
 2021-09-15 14:27:40 +08:00
Jon Lin
954b859e88 mtd: spinand: Enable MTD_NAND_BBT_USING_FLASH 
Using BBT in flash to avoid frequently flash operation for bbt info.
And it's secure to record the bad block info in bbt instead of
programing to the bad block with extremely unstable performance directly.

Change-Id: Icfe816c2c17ff3b747ce0a2512b1d9d6d0129fa0
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2021-09-15 10:45:22 +08:00
Jon Lin
9c5560bfce mtd: nand: add BBT using flash management strategy 
Support storing ram BBT into flash.

Change-Id: I42c2e91779e5385d959a4ce3807006074ae17483
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2021-09-15 10:45:22 +08:00
Doyle, Patrick
922d9619af UPSTREAM: mtd: nand: bbt: Fix corner case in bad block table handling 
In the unlikely event that both blocks 10 and 11 are marked as bad (on a
32 bit machine), then the process of marking block 10 as bad stomps on
cached entry for block 11.  There are (of course) other examples.

Signed-off-by: Patrick Doyle <pdoyle@irobot.com>
Reviewed-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Yoshio Furuyama <ytc-mb-yfuruyama7@kioxia.com>
[<miquel.raynal@bootlin.com>: Fixed the title]
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/774a92693f311e7de01e5935e720a179fb1b2468.1616635406.git.ytc-mb-yfuruyama7@kioxia.com
(cherry picked from commit fd0d8d85f7)
Change-Id: Ic3afc21e5f3e40950ed45036a41c57982983c70c
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2021-09-15 10:19:21 +08:00
Dingxian Wen
defc48455b media: i2c: lt6911uxc: add lt6911uxc HDMI to MIPI CSI-2 bridge driver 
1.cherry-pick from kernel-4.19
2.fix compile errors and adapt to kernel-5.10

Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com>
Change-Id: I5dc11d3c8a2559303d96b3206fafadb46f95ed0f
Signed-off-by: Jianwei Fan <jianwei.fan@rock-chips.com>
 2021-09-14 18:52:59 +08:00
Wyon Bi
515b6b6055 drm/bridge: analogix_dp: Add HBR2 support for RK3399 
Change-Id: I3999e4fa0b83ede5719f341d1e9a9a8797c7576b
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2021-09-14 18:47:09 +08:00
Wyon Bi
ae45df9576 drm/bridge: analogix_dp: Add support for SSC (Spread-Spectrum Clock) 
DPTX implements the programmable SSC down-spreading with up to
0.5% modulation amplitude and 30k/33k modulation frequency.

Change-Id: I2c3eae8f27c84eb1b22eac8973691e0276c1588e
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2021-09-14 18:47:09 +08:00
Sandy Huang
6e28f80f94 drm/rockchip: drv: sync with linux-4.19 
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Iaaea4f8067fbded3c135b5a992134c77d7b0bf05
 2021-09-14 10:02:10 +08:00
Zhen Chen
9245f41397 MALI: remove drivers/gpu/arm/bifrost_for_linux/ 
Change-Id: Ib91cbcc1d1413bdd9510661ffdd38dd72d984c56
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
 2021-09-14 09:58:48 +08:00
Zhen Chen
a8c5470313 MALI: remove definitions of MALI_BIFROST_FOR_ANDROID and MALI_BIFROST_FOR_LINUX 
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
Change-Id: Idd03a830e62582fe738919b7ef4d43163e9cdcb1
 2021-09-14 09:58:48 +08:00
Zhen Chen
27e243742d arm64: configs: rockchip: not to use CONFIG_MALI_BIFROST_FOR_LINUX 
No need to use CONFIG_MALI_BIFROST_FOR_LINUX
after px30/rk3326 Android and Linux device
use the same bifrost_device_driver "drivers/gpu/arm/bifrost".

Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
Change-Id: Ia4c9c79be2c10d5d708a8ea1bb4bc5d49c97267b
 2021-09-14 09:29:47 +08:00
Zhen Chen
766e61421d MALI: remove MALI_MIDGARD_FOR_ANDROID and MALI_MIDGARD_FOR_LINUX 
Because they are no longer useful,
after rk3288/rk3399 Android and Linux device
use the same midgard_device_driver "drivers/gpu/arm/midgard".

Change-Id: I7ccc3c99fdfdde5a0ea12a7f3e1931fd5f1ce4cb
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
 2021-09-14 09:29:47 +08:00
William Wu
5503f3c977 arm64: dts: rockchip: rk3568: disable receiver detection in P3 for usb 
RK3568 USB DWC3 controllers require to disable receiver detection
in P3 for correct detection of USB devices. And this quirk to set
the GUSB3PIPECTL.DISRXDETINP3, then the DWC3 core will change the
PHY power state to P2 and then perform receiver detection. After
receiver detection, the DWC3 core will change the PHY power state
to P3 state.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Iaad3f7ce2c4dee1788539781e3bcfbb39458f5d6
 2021-09-14 09:26:54 +08:00
William Wu
dde6656910 usb: dwc3: core: fix duplicate phy init when switch device 
According to the programming guide, it needs to reset the
device with DCTL.CSftRst when switching from host to device.
The current code use dwc3_core_soft_reset() to do DCTL.CSftRst,
it will also duplicate phy init which has been done in runtime
resume routine, this cause the phy init/exit operations are
unbalanced.

Without this patch, the dwc3 gadget resume fail on RK3568 EVB1
with the following log:
dwc3 fcc00000.dwc3: failed to enable ep0out

It's because that the init_count of usb3 phy is not 0 when
resume, so the dwc3 fail to call usb3 phy init, and the 3.0
pipe clock is not be running.

Fixes: b48bcb27ae ("FROMGIT: usb: dwc3: core: Do core softreset when switch mode")
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I58ec26f9f007c94f8979eeeb9a9d683c6db9548f
 2021-09-14 09:26:54 +08:00
Sugar Zhang
6e24506fce UPSTREAM: ASoC: dt-bindings: rockchip: Convert pdm bindings to yaml 
This patch converts pdm bindings to yaml.

Change-Id: Iafb212aa94ae63279a0817df55c569186f25fa66
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1630675438-3418-2-git-send-email-sugar.zhang@rock-chips.com
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 8ece5ef67e)
 2021-09-13 20:02:44 +08:00
Sugar Zhang
6a572fa08d UPSTREAM: ASoC: dt-bindings: rockchip: pdm: Document property 'rockchip,path-map' 
This is an optional property to describe data path mapping.

Change-Id: Ia35e60279d60555a10128cc808eb4c702f15173e
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1630675438-3418-1-git-send-email-sugar.zhang@rock-chips.com
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit b2527dcd65)
 2021-09-13 20:02:30 +08:00
Sugar Zhang
8a1487b2e1 UPSTREAM: ASoC: rockchip: pdm: Add support for path map 
This patch adds property 'rockchip,path-map' for path mapping.

e.g.

"rockchip,path-map = <3 2 1 0>" means the mapping as follows:

  path0 <-- sdi3
  path1 <-- sdi2
  path2 <-- sdi1
  path3 <-- sdi0

Change-Id: I231fde5a7bc92372b1b6cf723a5941ea6dc138a0
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Link: https://lore.kernel.org/r/1630675410-3354-5-git-send-email-sugar.zhang@rock-chips.com
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 13e6e042a6)
 2021-09-13 20:02:11 +08:00
Sugar Zhang
9d7d74dfc2 UPSTREAM: ASoC: dt-bindings: rockchip: Add binding for rk3568 pdm 
This patch documents for rk3568 pdm.

Change-Id: I558908d681c01a9389d56ea2341beed3bdb43a86
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1630675410-3354-4-git-send-email-sugar.zhang@rock-chips.com
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit f80e5a14ac)
 2021-09-13 20:01:56 +08:00
Sugar Zhang
f8606ea7b5 UPSTREAM: ASoC: rockchip: pdm: Add support for rk3568 pdm 
This patch adds compatible for rk3568 which is the same
with rv1126.

Change-Id: Iaab427da1bd39bb33c43f726324a50e12a3d7a11
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Link: https://lore.kernel.org/r/1630675410-3354-3-git-send-email-sugar.zhang@rock-chips.com
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit d00d1cd4ab)
 2021-09-13 20:01:42 +08:00
Sugar Zhang
f9dd1f7957 UPSTREAM: ASoC: dt-bindings: rockchip: Add binding for rv1126 pdm 
This patch documents for rv1126 pdm.

Change-Id: If2bf8cdc588a7dd17361f43aa9c9974e06e8e1ff
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1630675410-3354-2-git-send-email-sugar.zhang@rock-chips.com
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 49a7a625ad)
 2021-09-13 20:01:26 +08:00
Sugar Zhang
f305dfb553 UPSTREAM: ASoC: rockchip: Add support for rv1126 pdm 
This patch adds support for rv1126 pdm controller which
redesign cic filiter for better performance.

Change-Id: I78f8303f398762e032448c2d13969db7e704df72
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Link: https://lore.kernel.org/r/1630675410-3354-1-git-send-email-sugar.zhang@rock-chips.com
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit d269aa2ab9)
 2021-09-13 20:00:50 +08:00
Sandy Huang
df9559ce24 drm/rockchip: driver: add to get dclk pll source 
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I8f5f48a51d5ffa70312c142511aebe498f8eb796
 2021-09-10 19:46:09 +08:00
Andy Yan
1b6d9a91b2 drm/rockchip: vop2: Use clipped src/dst coordinates 
Some linux app(cusor) may set negative coordinates(crtc_x/y)

And some linux app(mpv) may set coordinates outside the screen.

These are both unsupported on rockchip vop.

so we use clipped coordinates here.

Change-Id: I63288cf9120cea75e784d49bc88b591f243e7d8d
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
 2021-09-10 19:26:32 +08:00
Andy Yan
a9a9527002 drm/rockchip: Use a standalone mutex_lock protect planes configuration 
Fix a deadlock on commit_lock when flush commit_work on async
commit mode:
mutex_lock(&private->commit_lock);
	flush_work(&private->commit_work);
		rockchip_atomic_commit_complete
			mutex_lock(&prv->commit_lock);
        			drm_atomic_helper_commit_planes(dev, state, true);

[root@RK356X:/]# echo w  > /proc/sysrq-trigger
[73134.630331] sysrq: Show Blocked State
[73134.630406]   task                        PC stack   pid father
[73134.630544] weston          D    0   585      1 0x00000000
[73134.630584] Call trace:
[73134.630648]  __switch_to+0xc0/0x124
[73134.630698]  __schedule+0x6f0/0x778
[73134.630739]  schedule+0x70/0x84
[73134.630779] [root@RK356X:/]#  schedule_timeout+0x4c/0x3d0
[73134.630817]  wait_for_common+0xe0/0x17c
[73134.630844]  wait_for_completion+0x28/0x34
[73134.630878]  __flush_work+0x118/0x1ac
[73134.630918]  flush_work+0x24/0x30
[73134.630961]  rockchip_drm_atomic_commit+0x154/0x220
[73134.631005]  drm_atomic_nonblocking_commit+0x54/0x60
[73134.631047]  drm_atomic_helper_page_flip+0x6c/0xa8
[73134.631089]  drm_mode_page_flip_ioctl+0x368/0x420
[73134.631119]  drm_ioctl_kernel+0x8c/0xfc
[73134.631166]  drm_ioctl+0x328/0x3bc
[73134.631207]  vfs_ioctl+0x58/0x68
[73134.631245]  do_vfs_ioctl+0xb4/0x9d4
[73134.631280]  ksys_ioctl+0x50/0x80
[73134.631317]  __arm64_sys_ioctl+0x28/0x38
[73134.631360]  el0_svc_common.constprop.0+0xe8/0x168
[73134.631389]  el0_svc_handler+0x70/0x8c
[73134.631435]  el0_svc+0x8/0xc
[73134.631497] kworker/3:1     D    0   823      2 0x00000028
[73134.631557] Workqueue: events rockchip_drm_atomic_work
[73134.631597] Call trace:
[73134.631643]  __switch_to+0xc0/0x124
[73134.631670]  __schedule+0x6f0/0x778
[73134.631711]  schedule+0x70/0x84
[73134.631749]  schedule_preempt_disabled+0x14/0x1c
[73134.631786]  __mutex_lock.isra.1+0x2c4/0x430
[73134.631824]  __mutex_lock_slowpath+0x24/0x30
[73134.631862]  mutex_lock+0x40/0x4c
[73134.631902]  rockchip_atomic_commit_complete+0xa0/0x124
[73134.631930]  rockchip_drm_atomic_work+0x20/0x30
[73134.631958]  process_one_work+0x200/0x330
[73134.631997]  process_scheduled_works+0x44/0x48
[73134.632037]  worker_thread+0x26c/0x2fc
[73134.632075]  kthread+0x120/0x130
[73134.632113]  ret_from_fork+0x10/0x18

Change-Id: Ia571c077f2d88854f9f568bb1693365e154d1e6c
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
 2021-09-10 19:26:32 +08:00
Sandy Huang
befd77968f Revert "drm/rockchip: vop2: Fix yuv 10 bit on cluster" 
This reverts commit 75cc68bce9.

From the latest code tests, this commit is not required.

Change-Id: Iad8e43fe119dee15de5e9b517df25a41fa71742c
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
 2021-09-10 19:03:39 +08:00
Sandy Huang
06aa7db349 drm/rockchip: vop2: add support yuv afbc format 
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I9e50c3b2ff57019c24aae77ca698d229204994ae
 2021-09-10 19:03:32 +08:00
Sandy Huang
a0b4d1fa92 drm/rockchip: driver: add interface to get format bpp 
drm_format_info can't offer yuv afbc bpp info, so we add this
interface to replenish it.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ib4d5f804b2ccdc20909420acd4911aa159d5a6fc
 2021-09-10 19:02:02 +08:00
Sandy Huang
fa6c7f1111 drm/rockchip: vop: sync with linux-4.19 for rk3399 vop 
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I7f703780d86ee964051a3ad2896745b34e852ccb
 2021-09-10 18:52:33 +08:00
Tao Huang
bcbc992aaa clk: rockchip: rk3308: Call rockchip_soc_id_init() on init 
clk init on time_init() which is before pure_initcall.
So call rockchip_soc_id_init() before call soc_is_rk3308b().

Change-Id: Iece3673bc7309ef9193df99f2a95e4b930613a3e
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
 2021-09-10 18:39:50 +08:00
Tao Huang
f08ca43b85 soc: rockchip: cpuinfo: Export rockchip_soc_id_init() function 
Allow rockchip_soc_id_init() called before pure_initcall.

Change-Id: Ie0d3a18e96df02c2d6ab4aa3e17ea102685cd0c4
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
 2021-09-10 18:39:50 +08:00
Simon Xue
5f5fd055a7 arm64: dts: rockchip: rk3588s: add decompress node 
Change-Id: I641f2ecdd1f08b60b50f8dac9a1647430474bd98
Signed-off-by: Simon Xue <xxm@rock-chips.com>
 2021-09-10 16:54:37 +08:00
Jon Lin
30e7c5bd44 drivers: rkflash: Support new SPI Nand devices 
GD5F1GQ4UExxH, W25N512GVEIG, SGM7000I-S24W1GH

Change-Id: Ib9e5422c3f57ef80e60fc6847d0ba9e1dd55dc3b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2021-09-10 10:49:08 +08:00
Jon Lin
7418744b59 drivers: rkflash: Add mutex for deinit ops. 
Change-Id: I477c161cb22f58263963a4d8e0d08eaeda676f69
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2021-09-10 10:48:16 +08:00
Jon Lin
e492952e0c drivers: rkflash: support new spiflash 
Add F35SQA001G, W25Q128JWSQ, XT25F64F, P25Q32SL, GM25Q128A
Change XT25F256BSFIGU, MX25U51245G

Change-Id: Ib9f60efbd3aad72044b7f3b0ee5a1a93333f0005
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2021-09-10 10:48:06 +08:00
Jon Lin
50947be187 drivers: rkflash: Add RK_SFTL configuration 
Avoid adding redundant FTL code to SPI Nand MTD case.

make ARCH=arm rv1126_defconfig test, size -t drivers/rkflash/built-in.a
the former size:
CONFIG_RK_SFC_NAND=y
CONFIG_RK_SFC_NAND_MTD=y
CONFIG_RK_SFC_NOR=y
CONFIG_RK_SFC_NOR_MTD=y
text    data     bss     dec     hex filename
83237    2757   23716  109710   1ac8e (TOTALS)

after adjust:
31677    2705    3624   38006    9476 (TOTALS)

For Nor only:
CONFIG_RK_SFC_NOR=y
CONFIG_RK_SFC_NOR_MTD=y
19350    1237    2568   23155    5a73 (TOTALS)

Change-Id: I46186393de26512566cc62ceb1490ef35a70be1d
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2021-09-10 10:48:06 +08:00
Jon Lin
d047f245b8 drivers: rkflash: Ajudst the dll strategy 
1.max_dll_cells is 0x1FF when sfc_ver_4
2.sfc_set_delay_lines to zero means disable dll
3.bypass dll training when there is no device
4.Adjust the dll_value to from the middle of the dll window to
the better one
5.Change RKSFC_DLL_THRESHOLD_RATE to ">50MHz"

Change-Id: Ibd669420899925272c74e190fee8c62c09db8d14
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2021-09-10 10:48:06 +08:00
Jon Lin
75b1344eee drivers: rkflash: Notice it when the storage device is not support 
When the related print appears, it means that the SDK is too old
and the storage driver needs to be updated.

Change-Id: I63f45fba4cf52108c628f225ee23aa0819ca256f
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2021-09-10 10:48:06 +08:00
Jon Lin
067686d494 drivers; rkflash: Support new devices 
W25N04KVZEIR, DS35Q2GB-IB, EM73C044VCF-H, XT26G11C, MT29F1G01ABA,
F50L1G41XA, JS28U1GQSCAHG-83

Change-Id: I38a16e26dea1624a4e101d7f965f9abfe44a3821
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2021-09-10 10:48:06 +08:00
Kever Yang
89454d9cfc arm64: dts: rockchip: rk3588: add pcie controller support 
The rk3588 supports 5 controllers:
- 1 pcie3x4;
- 1 pcie3x2;
- 3 pcie2x1(2 of them also available in rk3588s);

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: Icae3a5539ace233141ff7f89600d17758be7fa5c
 2021-09-10 09:48:10 +08:00
Kever Yang
e1fdb69cd8 arm64: dts: rockchip: rk3588s: add pcie2 controller 
RK3588s supports 2 pcie2 controllers which use the phy combo to sata and
usb3.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: Id97957ef5341e9ab61af861b2b6194c056ad5835
 2021-09-10 09:48:10 +08:00