According to the advice of the IC,
setting the PMU_GPU_PWRDW/PWRUP_CNT regs 6 cycel(250ns) for RK3399 SOC.
Change-Id: I0449069a3b5035bd0442fcd74b645de9480a1d89
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
These clock rate are used for HDMI display.
Change-Id: I4742dcfe8ddedfa6b86c38ce03bcaa5c28b34c4e
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
When we use the MIPI screen, the driver will unprepare and disable
the phy_cfg, it will diable its parent pclk_vio:
dw_mipi_dsi_phy_init
--> clk_disable_unprepare
--> clk_disable
--> clk_core_disable(core->parent)
The pclk_vio supply power for pclk_vio_grf, hence, disable pclk_vio_grf will
cause other drivers failed to operate GRF.
Change-Id: I6d5bd27b9478da09209130f1fd5a62c0d4bb1785
Reported-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
We recommend, VOP0 is the main screen, VOP1 is a sub screen,
only VOP0 is able to re-set parent (VPLL) rate.
Change-Id: If40f95ce18e73477df8f7f031013333a603d5eb2
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Because frac div need to more than 20 multiple between the numerator
and denominator, but we need to be fit many HDMI/DP freqs and may
bring serious jitter when the dclk_vopx below the dclk_vopx_frac.
Therefore, we can select dclk_vopx below the dclk_vopx_div directly.
Change-Id: If3d9051211f0b160a507f0942667796f043f4ec2
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
We hope to be able to HDMI/DP can obtain better signal quality,
therefore, we move VOP pwm and aclk clocks to other PLLs, let
HDMI/DP phyclock can monopolize VPLL.
Change-Id: Ib715f9d29c0743d113f9f74886ff3921c9e0a327
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
We need to declare that we enable all NOCs which are critical clocks
always and clearly and explicitly show that we have enabled them at
clk_summary.
Change-Id: I859664692b4d1bb0dda0ee38295dfcbc3cc70019
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The reserved root blocks is not enough for booting Android due to
the limit of 0.2% if the fs size too small. so we add a new mini-
mum limit is 128MB.
Change-Id: I5af3b182001d27e4d18b4090c5270bbb2ac6253b
Signed-off-by: Cliff Chen <cliff.chen@rock-chips.com>
The f_blocks of statfs include file system overhead，it is not normal
usage of Posix.
Change-Id: If481626b08c05290626938586e2dc721690f1a91
Signed-off-by: Cliff Chen <cliff.chen@rock-chips.com>
If cmd is empty in get_reboot_mode_magic, we should return normal magic.
Change-Id: I10931adc49e33f72ae73d9471159f82cc02ff0c0
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
rk3288 ohci doesn't actually work on hardware, so we
need to disable it in ohci-platform driver.
Change-Id: I72750edda67358ff1e8fe66047bf60420500997e
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Like the runtime PM support patch of ohci-platform, we
add the same basic runtime PM for ehci-platform.
Conflicts:
drivers/usb/host/ehci-platform.c
Change-Id: I84cbb15dd393e6af69b4cf6887f1628e2cba4999
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Some EHCI controllers use usic phy (e.g rk3399/rk3288),
in order to enable these controllers, we need to set
some additional EHCI vendor-specific registers.
Support this feature in device tree when using the ehci
platform driver by adding a new property for it.
Conflicts:
drivers/usb/host/ehci-platform.c
Change-Id: I279ccfdb5866df49828825bfd41b39fcd58a2832
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
For the hardware bug of RK3288 OHCI, we use commit cfe6f1dd57
("usb: ehci: add rockchip relinquishing port quirk support") to fix
it previously. However, it have been ineffective after upstream commit
94c43b9897 ("USB: Check for dropped connection before switching to
full speed") was merged due to the condition of relinquishing port was
changed.
This patch adds an additional condition for the previous commit to ensure
no relinquish port quirk can take effect for RK3288 EHCI.
Change-Id: I0630265e101afb349816955e069e1c121745ac08
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
rk3288 and rk3288w use the same dts which includes no relinquish
port quirk, however rk3288w ohci can work well, so we need to add
an additional condition to disable ohci only for rk3288.
Change-Id: Ic2bd0ce577cbebe7ae2cf1b153f9e46935022f77
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Add a quirk to support rockchip relinquishing port from abnormal ohci
to ehci when FS/LS devices plug in.
To support this function, the rockchip-relinquish-port property must be
specified in ehci node of dt.
Conflicts:
drivers/usb/host/ehci-platform.c
Change-Id: I91b58905132282ef2a836d54a1c7ace1e334d119
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This fixes uninitialized variable introduced by commit ddd2e87ad4
("dmaengine: pl330: add support for interlace size config")
Change-Id: Ib1bbec21053fbcccf85a339d8ed7eec0bbe77727
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
It's found a new r8169 ethernet card with a device ID of
0x0000 read from its config header which wasn't in the
ID tables of r8169. Add it in order to probe this card.
Change-Id: I27c542a10cc571a6e1a4e7a8af62ce560b8b1fc4
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
PX30_GRF_SOC_CON5 is intended for postponing the auto switch
of pinmux from SDMMC to JTAG after removing the SD cards.
However, the default value is too small to meet the actual
requirement. Increase this value to 5 seconds currently.
Change-Id: I18fafe07822b81d9cd448ab71c1f0e49a75db357
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Rockchip platform now not only use dw_mmc but also
the sdhci-of-arasan could be used as emmc. So we need
to add its dependency when setting emmc_disk flag.
Change-Id: I84f99657b874a15e60063b1b4ff94fd90cc191c3
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
We observed the failure of initializing card after resume
accidentally. It's hard to reproduce but we did get report from
the suspend/resume test of our RK3399 mp test farm .Unfortunately,
we still fail to figure out what was going wrong at that time.
Also we can't achieve it by retrying the host->f_init without falling
back it. But this patch will solve the problem as we could add some log
there and see that we resume the mmc card successfully after falling
back the host->f_init. There is no obviousside effect found, so it seems
this patch will improve the stability.
[ 93.405085] mmc1: unexpected status 0x800900 after switch
[ 93.408474] mmc1: switch to bus width 1 failed
[ 93.408482] mmc1: mmc_select_hs200 failed, error -110
[ 93.408492] mmc1: error -110 during resume (card was removed?)
[ 93.408705] PM: resume of devices complete after 213.453 msecs
Change-Id: I5b24cb84a223394392450a1f10d8bbacb9e1006e
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Let's keep genpd for sdhci alive while entering deep
sleep which gte me out of yapping around.
Change-Id: I0da20b417621d277745bafd53d1ee461aae72e11
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Since HDMI needs clock rate 74.25MHz, so plls must support
a multiple of it.
For Rockchip rk3368 pll has better jetter with 1188MHz, so
add 1188MHz support.
Change-Id: I68c7333ae076ecabf8637298ee8ca43149cb17d1
Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add dt-binding for mipi dsi 24M clock, and use it.
Change-Id: I1f4dfac958b8b5dacfa6da02151dc3d6a2bd27a7
Signed-off-by: Jianqun xu <jay.xu@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The DPHY(DSI PHY) in Rockchip rk3368 supports MIPI/TTL/LVDS
mode. Use the clock IDs (PCLK_DPHYRX and PCLK_DPHYTX0) for
DPHY clocks.
Change-Id: I6a133d6da839d6545e507f38b361b3457e5ff3ee
Signed-off-by: Jianqun xu <jay.xu@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Programmable THRE Interrupt mode in order to increase system
performance.
Change-Id: Ic1ef9ecae0c6feb00170ad97ee3c6245ca3bf068
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Most SOCS have only 8 or 6 channels, but have more than 16
peripherals. If those peripherals work together, some
fails to request dma channel, because there are no enough
channels. And maybe it's unnecessary to use dma for uart
tx. It is necessary for uart rx when hardware auto flow
control is not used.
&uart0 {
dma-names = "!tx", "rx"; // disable uart tx with dma
status = "okay";
};
Change-Id: Ia74477514ba57300a4d19a5c2565ae7b5b8ab521
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
To avoid "too much work for irq" issue, cherry pick the the patch.
It reads the RBR to clear the time out interrupt, but sometime the
rx fifo may be not empty while cpu reads the RBR. Which would cause
the data lost.
patch for "too much work":06451e93ab59e5b1843c29cbb468a274f4919563
By the way, current patch can't get rid of the risk entirely, so I
try a lot to solve it. Unfortunately, I only got the phenomenon that
lower pclk can reduce the probability. And I check the dw data sheet,
it has pclk and sclk, so there is synchronization problem. But it
only requires (slck < 4*pclk).
Change-Id: I01a36c689b43310294c45294abcf4982f5ddf2af
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Add wakeup-source to uart dts node to enable uart
wake up system when it receives data.
Change-Id: If4e82a4d3dbaca708209553dc3693089864c782f
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
