shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-07 19:30:30 +09:00
Code Issues Packages Projects Releases Wiki Activity
843,908 Commits 55 Branches 2,486 Tags
5cdb722d419388be02cd9aa56ffd05547f3779d3
Commit Graph

843908 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Algea Cao
5cdb722d41 drm/rockchip: hdmi: Add rk3228 hpd interface 
Add rk3228 hpd set up and read interface.

Change-Id: Ie658f501e04376eb4b67ff78b0cfaeb9220f8189
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
 2019-07-22 10:42:40 +08:00
WeiYong Bi
48d9d7f2b2 drm/rockchip: hdmi: Add support for rk3228 
RK3228 uses the Synopsys DWC HDMI TX controller and the INNO HDMI PHY to
enabling the integration of a complete HDMI Transmmiter interface.

Change-Id: I90f997968fb2de4165a31216c8aee8213089eab5
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
 2019-07-22 10:42:40 +08:00
WeiYong Bi
f4a0a4155b drm/rockchip: dw_hdmi: Add support for rk3368 
Change-Id: I6a49447a5edd53013ed81875f351089793914f77
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
 2019-07-22 10:42:34 +08:00
Liang Chen
86379b37ce clk: rockchip: rk3328: set ddr clk with sip call 
We need use sip call to change ddr frequency.

Change-Id: I6ad4516306f0cb7c3e0a7124c21ee9fedfd9d055
Signed-off-by: Liang Chen <cl@rock-chips.com>
 2019-07-19 19:28:33 +08:00
Sugar Zhang
eee2c022da arm64: configs: rockchip_defconfig: enable SND_SOC_ROCKCHIP_I2S 
Change-Id: I905384a8d0b59a53824189ddcee4636e0670137b
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
 2019-07-19 19:27:09 +08:00
Sandy Huang
1aea43982f drm/rockchip: vop: add support mcu and gamma 
Change-Id: I02d093baaec6e363cadb6ef2b4943c00285c1cd7
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
 2019-07-19 19:24:24 +08:00
Sandy Huang
0848de283c drm/rockchip: vop: sync register define with linux 4.4 
Change-Id: I088a052319f91a3189b1c4811837c957daa56aef
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
 2019-07-19 19:24:17 +08:00
Sandy Huang
7d604e646f drm/rockchip: driver: DRM_MODE_CONNECTOR_Unknown type unsupport hotplug 
Change-Id: I3b8dc97e5bd6ae6a2877adaf82d4ef4f578f95db
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
 2019-07-19 14:24:34 +08:00
Sandy Huang
c86b7a8dd3 drm/rockchip: vop: add BCSH support function 
Change-Id: I17bcd5a07b93b3c68aa892606f886bcd3a7673a0
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
 2019-07-19 14:24:03 +08:00
Sandy Huang
19e2fb90cf drm/rockchip: vop: add support post scale 
Change-Id: I8d937b2659e4201a26e654b1f1aed1a9ea8405d1
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
 2019-07-19 14:23:34 +08:00
Sandy Huang
f4d66025c2 drm/rockchip: driver: correct rockchip_crtc_state->output_type 
Change-Id: I572170010e17a2a11cd650538cb09c18f82cf728
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
 2019-07-19 14:23:14 +08:00
Sandy Huang
2faecef993 drm/rockchip: dw_hdmi: init connector port for kernel logo 
Change-Id: If964f72aa8f242406145d8ac42a35ac0932f6f3f
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
 2019-07-19 14:22:23 +08:00
Sandy Huang
5212d8eb24 drm/rockchip: vop: add more output type support 
Change-Id: I9fb3023400086fe83326c039e443daaa35be7b9b
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
 2019-07-19 14:22:07 +08:00
Sandy Huang
1a5de0dbf0 drm/rockchip: vop: set frame start to field start for interlace mode 
In interlace mode(480i60hz) the frame rate is 30hz, this is too low and
lead to CTS test failed, so we use field start interrupt instead of
frame start, and the vsync will update to 60hz.

Change-Id: If73fb2b04dbd6749cc7cf899234a9f1e2283519e
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
 2019-07-19 14:21:20 +08:00
Sandy Huang
6b2cb2ade2 drm/rockchip: vop: add support CSC 
Change-Id: I4ed359529825fc6c8d91460e89aa48ec9ed3e13f
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
 2019-07-19 14:20:56 +08:00
Sandy Huang
265d4bcbae drm/rockchip: driver: set loader_protect when in kernel logo on 
protect restore_fbdev_mode in kernel logo on until userspace
power on.

Change-Id: I561d9eaa3a931471cdc81b41f6c0a7db28588ba0
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
 2019-07-19 14:19:59 +08:00
Sugar Zhang
df7d49af42 ASoC: codecs: add support for rk3328 
switch to use snd_soc_component.

Change-Id: I66ff61c18fe70135fd7ac0569954263743263a3a
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
 2019-07-19 11:37:21 +08:00
Sandy Huang
f5d50a13b7 drm: add loader_protect for restore_fbdev_mode 
the following flow is conflict with kernel logo display:
so we ignore the restore_fbdev_mode_atomic when in kernel
logo on state.

[    0.861904] vop_plane_atomic_update+0x2604/0x390c
[    0.861913] drm_atomic_helper_commit_planes+0x158/0x1d8
[    0.861922] rockchip_atomic_commit_complete+0x94/0xf0
[    0.861930] rockchip_drm_atomic_commit+0x1c0/0x1f8
[    0.861938] drm_atomic_commit+0x6c/0x84
[    0.861948] restore_fbdev_mode_atomic+0x1a8/0x224
[    0.861956] restore_fbdev_mode+0x60/0x168
[    0.861965] drm_fb_helper_restore_fbdev_mode_unlocked+0x74/0xb0
[    0.861974] drm_fb_helper_set_par+0x80/0xa0
[    0.861983] drm_fb_helper_hotplug_event+0x10c/0x124
[    0.861991] rockchip_drm_output_poll_changed+0x54/0x64
[    0.862000] drm_kms_helper_hotplug_event+0x48/0x70
[    0.862009] output_poll_execute+0x1c4/0x214
[    0.862018] process_one_work+0x208/0x3bc
[    0.862027] worker_thread+0x214/0x318
[    0.862035] kthread+0x120/0x128
[    0.862043] ret_from_fork+0x10/0x18

Change-Id: I8e9874659e9f6b3a29e34f247855b73faf42fde0
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
 2019-07-19 11:11:52 +08:00
Sandy Huang
3cbcf9bdbd Revert "arm64: dts: rockchip: rk3399: delete vop iommu PD" 
This reverts commit 460dc0405a.

Change-Id: Ie25c20e79c57c4e1bc678774ad09b60fc4a135dc
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
 2019-07-19 11:11:21 +08:00
Elaine Zhang
d45556ed94 soc: rockchip: power-domain: Add protection for some special pd during startup 
Use DOMAIN_RKXX_PROTECT to keepon the pd during startup.

Change-Id: I526b97ec273e056e703b6e187d0e6ffec44e730c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-07-19 10:11:27 +08:00
Mark Yao
58d4433d5a drm: of: don't mask possible_crtcs if remote-point is disabled 
Change-Id: I98d42ce5c9a5ed832e455a3d1fc88cf3ec717d69
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
 2019-07-11 15:35:39 +08:00
Wyon Bi
70e987f2a8 drm/rockchip: dsi: enable interrupt function 
Change-Id: I5003056c1b7244407310353547f065b13433f3d7
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2019-07-11 09:24:01 +08:00
Wyon Bi
b31e6c543c drm/rockchip: dsi: support non-continuous clock behavior 
This bit enables the automatic mechanism to stop providing clock in
the clock lane when time allows.

Change-Id: Ia3d85589f54adcf6206ee7ded32624b8e92936af
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2019-07-11 09:23:59 +08:00
Wyon Bi
4d3459c8ac drm/rockchip: dsi: support dual-link mode 
Display Pipeline:

1) dual-channel mode

              --> dsi0 --> dphy_tx0 -->
             /                 !       \
vopl/vopb -->              dphy_pll     --> panel
             \                 !       /
              --> dsi1 --> dphy_tx1 -->

2) dual-link mode

vopb/vopl --> dsi0 --> dphy_tx0 --> panel0
                           !
                       dphy_pll
                           !
vopl/vopb --> dsi1 --> dphy_tx1 --> panel1

Change-Id: Iddbea22f121959e4afa969d74549d8fb66ab09f1
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2019-07-11 09:23:58 +08:00
Wyon Bi
4f6e785d70 drm/rockchip: dsi: Add support for adapted command mode (Auto mode) 
Three operating mode are available to convey the graphical data
to the display:
- Video mode streams over the high-speed link the RGB data and the
  associated synchronization signals directly generated by the LCDC.
  The streaming starts as soon as the DSI Host and the LCDC are enabled.
  This continuous refresh is the best way to interface with a display
  without Graphics RAM.
- APB command mode sends commands over the high-speed link for
  configuration as it is done using a legacy serial interface (SPI).
  The commands are launched using the DSI Host APB interface.
- Adapted command mode is the best way to interface with a display
  having its own internal Graphics RAM. The DSI Host captures only
  one full frame coming from the LCDC and transforms it into a series
  of write commands to update the display Graphics RAM.

Change-Id: Id2a9ccf71997f42126a3719bc349576013970158
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2019-07-11 09:23:56 +08:00
Wyon Bi
44246d97de drm/rockchip: dsi: Add support for dual channel mode 
Change-Id: I6fa8427c55b3efb611cf67087283bee7b95a4fd5
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2019-07-11 09:23:55 +08:00
Wyon Bi
fb45f3f26c drm/rockchip: dsi: support EoTp feature 
In order to enhance the overall robustness of the system, DSI defines
a dedicated EoT packet (EoTp) at the protocol layer for signaling
the end of HS transmission. For backwards compatibility with earlier
DSI systems, the capability of generating and interpreting this EoTp
can be enabled or disabled.

Change-Id: Iddc7e82a7e3e47dea94846fbb771da8fddc0fda3
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2019-07-11 09:23:54 +08:00
Wyon Bi
b42258535e drm/rockchip: dsi: rework dw_mipi_dsi_host_transfer 
Add full support for MIPI DSI Processor-to-Peripheral transaction types.

Change-Id: Ic0ebb55908c95541b7356d4796869202aa3ffcdc
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2019-07-11 09:23:52 +08:00
Wyon Bi
23f2b6023b drm/rockchip: dsi: fix pll clock setting 
Change-Id: I4132fd04b1b0788d5a0db2f5c7b2831e204286c4
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2019-07-11 09:22:30 +08:00
Wyon Bi
d13ab488bb drm/rockchip: dsi: Fix improved D-PHY data lanes timing 
Change-Id: Ibc8dfd6bf208407117156dc36539d95740b213d8
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2019-07-11 09:20:44 +08:00
Wyon Bi
8f2cf6a08d drm/rockchip: dsi: Add encoder atomic_mode_set callback 
Change-Id: If61bdfe00ef5258db19fe09b9c07ea369586a4bf
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2019-07-11 09:20:43 +08:00
Wyon Bi
c8b9eed1db drm/rockchip: dsi: fix phy power-on sequence 
Change-Id: I0ceaedb71776747e8951a75409bcc2521252dd18
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2019-07-11 09:20:42 +08:00
Wyon Bi
a516aaec11 drm/rockchip: dsi: Convert to use regmap 
Change-Id: Ia697fce3f51cf0278f37ac0e809173ebca076d6b
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2019-07-11 09:20:41 +08:00
Wyon Bi
b58b0c40c4 drm/rockchip: dsi: Add a better description for dw_mipi_dsi_plat_data 
Change-Id: I6a149747a12bbd1c3e84cd33769ed453770353af
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2019-07-11 09:20:35 +08:00
Wyon Bi
a328ea76f9 drm/rockchip: dsi: code style cleanup and fixes 
Change-Id: Ia01db15cffd2a82e756d19d048e75a416b11b6be
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2019-07-11 09:18:17 +08:00
Wyon Bi
a616fed5f8 Revert "drm/rockchip/dsi: enable the grf clk before writing grf registers" 
This reverts commit 5bc07b1569.

Change-Id: Ifb9363ab30c139f41e2ee69fba97c9ec5bfcca1b
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2019-07-11 09:11:19 +08:00
Wyon Bi
91a8fbc44b drm/panel: simple: handle small delay durations more precisely 
Since msleep is based on jiffies the panel could take longer
than expected. So use msleep for values greater than 20 msec
otherwise usleep_range.

Change-Id: Ib03c6e381b44a31dd57aeaaa3a88a459578de313
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2019-07-11 09:11:17 +08:00
Wyon Bi
405fb07849 drm/panel: simple: support transmit DSI packet 
Change-Id: I1a11ef4d914d161f354b783d833d5afb48bc3074
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2019-07-11 09:11:10 +08:00
Wyon Bi
968a5ee200 drm/panel: simple: Add reset gpio 
Change-Id: I12a4495a5897535b2a2fe8117a626ee7639dfef0
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2019-07-11 09:06:36 +08:00
Wyon Bi
0f36136db1 drm/dsi: Export mipi_dsi_device_transfer() 
Change-Id: I66cff30b42700c7aaf69ac7cdb8a92129244c6d7
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2019-07-11 09:06:35 +08:00
Sandy Huang
abb839cb1d drm/rockchip: vop: correct plane state 
Change-Id: I3ce0687041193ee88b4a28099de0341a95437349
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
 2019-07-05 13:02:45 +08:00
Sandy Huang
ae08a0e7ac dt-bindings: display: media-bus-format: Sync with include/uapi/linux/media-bus-format.h 
Change-Id: I1da14bc81a8652dcac5f0b85035f8f1bf6e71bfe
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
 2019-07-05 10:34:58 +08:00
Wyon Bi
47bcb41590 dt-bindings: display: media-bus-format: Sync with include/uapi/linux/media-bus-format.h 
Change-Id: I3f6deb2e264956205da725aa78f79ee7404d13a8
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2019-07-05 10:34:54 +08:00
Sandy Huang
d6eaf64098 media-bus: Add SRGB888 media bus format 
The output timing described at [1], focus at s888 mode and
s888 dummy mode:

[1] https://patchwork.kernel.org/patch/9992241/

Change-Id: I1bcc6d64ede243d89807acc7e842bcc7fd120c26
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
 2019-07-05 10:34:48 +08:00
Wyon Bi
9e885ddad0 media: Add MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA media bus code definitions 
This patch adds a new RGB media bus formats that describe
18-bit samples transferred over an LVDS bus with three
differential data pairs, serialized into 7 time slots,
using standard JEIDA data ordering.

Change-Id: Ia0bedd53e57aa34829a0d61b144aa99a1c98cffd
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2019-07-05 10:34:37 +08:00
Sandy Huang
5e547ad10b drm/rockchip: vop: use bpp instead of cpp for yuv 10bit format 
Change-Id: If5044a0631d5ed11f683072ca7c29a1c4f1f8384
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
 2019-07-05 10:25:38 +08:00
Sandy Huang
7c7b813de3 drm: add support for 10bit yuv format 
Change-Id: I16358258c574b296dafad85318f696134d4631cf
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
 2019-07-05 10:25:33 +08:00
Sandy Huang
e206a3aee7 drm/panel: Don't init gpio value at probe 
When enable display on loader, init gpio would change
gpio status, that would make screen flash.

Change-Id: I4b69a8d3d83c5bef09014c2134abaee6522a7046
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
 2019-07-05 10:22:01 +08:00
Algea Cao
6bd6c35e9d drm/rockchip: dw_hdmi: Support HDMI 2.0 YCbCr 4:2:0 
Some old code has too many conflicts with the upstream code,
so recombine and commit these changes.

Including these changes:
1.Support yuv420.
2.Limit rk3229/rk3328 max output resolution.
3.Support dynamically get input/out color info.
4.Introduce mpll_cfg_420.
5.use drm_mode_is_420 instead of DRM_MODE_FLAG_420_MASK.

Change-Id: I42462284b16f26b7adef0e9455903ee5fc71e432
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
 2019-07-03 19:38:32 +08:00
Finley Xiao
5e5845517a PM / devfreq: rockchip_dmc: Fix using smp_processor_id() in preemptible warning 
Fix this warning when DEBUG_PREEMPT is selected:
BUG: using smp_processor_id() in preemptible [00000000] code: devfreq_wq/46
caller is debug_smp_processor_id+0x1c/0x24
CPU: 4 PID: 46 Comm: devfreq_wq Tainted: G           O    4.4.179-gaa55fe4a4414 #71
Hardware name: Rockchip RK3399 Excavator Board (Linux Opensource) (DT)
Workqueue: devfreq_wq devfreq_monitor
Call trace:
[<ffffff800808866c>] dump_backtrace+0x0/0x228
[<ffffff80080888b8>] show_stack+0x24/0x30
[<ffffff80083c91a0>] dump_stack+0x88/0xb0
[<ffffff80083e11f0>] check_preemption_disabled+0xd4/0xfc
[<ffffff80083e1234>] debug_smp_processor_id+0x1c/0x24
[<ffffff80087a8ce0>] rockchip_dmcfreq_target+0x114/0x340
[<ffffff80087a5ff0>] update_devfreq+0x120/0x1b4
[<ffffff80087a60b8>] devfreq_monitor+0x34/0x8c
[<ffffff80080b3164>] process_one_work+0x23c/0x3d8
[<ffffff80080b3340>] process_scheduled_works+0x40/0x44
[<ffffff80080b3c8c>] rescuer_thread+0x174/0x26c
[<ffffff80080b9020>] kthread+0xdc/0xec
[<ffffff8008082ef0>] ret_from_fork+0x10/0x20
BUG: using smp_processor_id() in preemptible [00000000] code: kworker/u12:1/720
caller is debug_smp_processor_id+0x1c/0x24
CPU: 0 PID: 720 Comm: kworker/u12:1 Tainted: G           O    4.4.179-gaa55fe4a4414 #71
Hardware name: Rockchip RK3399 Excavator Board (Linux Opensource) (DT)
Workqueue: devfreq_wq devfreq_monitor
Call trace:
[<ffffff800808866c>] dump_backtrace+0x0/0x228
[<ffffff80080888b8>] show_stack+0x24/0x30
[<ffffff80083c91a0>] dump_stack+0x88/0xb0
[<ffffff80083e11f0>] check_preemption_disabled+0xd4/0xfc
[<ffffff80083e1234>] debug_smp_processor_id+0x1c/0x24
[<ffffff80087a8ce0>] rockchip_dmcfreq_target+0x114/0x340
[<ffffff80087a5ff0>] update_devfreq+0x120/0x1b4
[<ffffff80087a60b8>] devfreq_monitor+0x34/0x8c
[<ffffff80080b3164>] process_one_work+0x23c/0x3d8
[<ffffff80080b4064>] worker_thread+0x2e0/0x3a0
[<ffffff80080b9020>] kthread+0xdc/0xec
[<ffffff8008082ef0>] ret_from_fork+0x10/0x20

Change-Id: I11a2d4684cb3306124470692649c0041d7615f77
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2019-07-03 18:43:26 +08:00