The pin2dts tool has fixed some bugs, do generate the rv1126-pinctrl
codes with new tool.
Change-Id: Ie932397064bc8f0022cbdf9a6e8e4242cd4d8ad8
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
ov8858 checked unexpected sensor id, while ret may be 0;
thus it will continue register, but ov8858_global_regs
& supported_modes are still null pointer.
This results crash in ov8858_s_power function, when ov8858_global_regs
& supported_modes are called; so fix it.
Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: Idb65a593f526572f4a4423464a1daf0299a3aa5c
Reset the previous DLL settings left out from loader in case
of running initial booting with mismatch DLL settings.
Change-Id: Icba9ddcafc3969f7869a6ba31a017db6be0c885e
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
This patch fixes the bug of RV1126 USB crash when configed as
UVC + UAC + RNDIS + ADB. If we resize txfifo before opening
UAC stream, the maxpacket of epin will be the default value
1024 and txfifo will exceed the maximum limit.
Fixes: e658b2131e ("usb: dwc3: gadget: fix tx fifos resize for disabled eps")
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: I1e892b11a0bdda2877d3e17148867d21cb68238c
Test:
android.hardware.input.cts.tests.NintendoSwitchProTest#testAllKeys
android.hardware.input.cts.tests.NintendoSwitchProTest#testAllMotions
This config will enable the Nintendo Switch Pro controller driver.
Signed-off-by: Bian Jin chen <kenjc.bian@rock-chips.com>
Change-Id: I4a29d458c3a0d82dec33e4b3990888217d580298
Test:
android.hardware.input.cts.tests.NintendoSwitchProTest#testAllKeys
android.hardware.input.cts.tests.NintendoSwitchProTest#testAllMotions
This config will enable the Nintendo Switch Pro controller driver.
Signed-off-by: Bian Jin chen <kenjc.bian@rock-chips.com>
Change-Id: I3347b07b263559fccf0b94d4253f00cddfb547c6
ES7243E is 2-ch ADC with I2S interface for Microphone Array
Signed-off-by: Binyuan Lan <lby@rock-chips.com>
Change-Id: I3c61f5feccad9362e2859d7646e88a0e990c998c
RK3566 is a Soc from Rockchip, which embedded with quad
ARM Cortex-A55.
This patch add basic core dtsi file for RK3566.
Change-Id: Ide02369e6be3515fb7ec62bea4069f476374f897
Signed-off-by: Liang Chen <cl@rock-chips.com>
RK3288_GRF_GPIO6C_IOMUX address is 0x64, if not jugged type RK3288;
it will set rk3568 GRF_GPIO4A_IOMUX_H reg to 0x0 after resume.
then cause gpio4 a4/5/6/7 iomux abnormal.
Fixes: 8dca933127 ("pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resume")
Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: Icb7700ff63e3cb8ca46025e6efd260d91608f23f
post bcsh csc module need to know win overlay at yuv or rgb domain.
Change-Id: I246c22ddf0d02f48f515947a48ef058dca36c7a5
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Two sub windows in a cluster share same ctrl register bit.
Change-Id: I0a123fd3a1f63bbf0d6abea557e6024a99adb4cb
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
issues
cam_clkout0 correponding gpio4 A7 pinctrl may changed,
when wakedup from deep sleep. so artificial to set pinctrl.
Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: Iad200cbc6685cb18217a7577746bef122fa51574
YUV 10 bit config value on Cluster is different
with Esmart/Smart.
Change-Id: If334f347b6d1759650113b36327a49a850f03e0e
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
debug node is external debug
cspmu is coresight pmu
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: I4cfb9cb3c40fa5bce8feb868432ed5210783cdd5
debug node is external debug
cspmu is coresight pmu
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: If74d80ba30b007b0364d715ae76624a30fe4a959
RK356x doesn't support EDPCSR, but support pmupcsr of pmu
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: If588f4cc11909a57ded61937e4266ab7fd3fab17
pipe clock settings were done before PCIe's and SATA's catch-all
pipe settings. So it would be covered by con1_for_pcie and
con1_for_sata. Fix this by moving pipe clock settings to the end.
Change-Id: I19a8943b6a99d8e4ef198345ec3f62bdac491c58
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
