-# CONFIG_AUDITSYSCALL is not set
-# CONFIG_ROCKCHIP_ONE_INITRD is not set
-CONFIG_RTL8723CS=m
-CONFIG_RTL8821CS=m
-CONFIG_RTL8822BS=m
-CONFIG_LTE=y
-CONFIG_LTE_RM310=y
-CONFIG_RK3368_THERMAL=y
-CONFIG_REGULATOR_DIO5632=y
-CONFIG_VIDEO_GC0312=y
-CONFIG_VIDEO_OV5648=y
-CONFIG_VIDEO_VM149C=y
-CONFIG_SND_SOC_ROCKCHIP_RT5651=y
-CONFIG_SDIO_KEEPALIVE=y
-CONFIG_POWERVR_ROGUE_N=y
-CONFIG_RK3368_MBOX=y
-CONFIG_RK3368_SCPI_PROTOCOL=y
-CONFIG_SDCARD_FS=y
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I9ad2e626d1d7125830fca09791158ad6cd8910fc
This adds the necessary data for handling otp on the rk3528.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I1ffe83be9f5497e7503876b9b3916a880811ed9d
Adding HDCP1.3 and HDCP2.2 function support. For support
HDCP2.2, It also need prepare hdcp controller driver and
userspace host library.
Considering that HDCP2.2 is more secure than HDCP1.4, It
preferred to use HDCP2.2 if HDCP2.2 capable is be setup.
Only when the HDCP2.2 is not supported(or HDCP2.2 is failed)
and Content Type is Type0, HDCP1.3 will work.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Icb6e371b5b798cc2fe2233656ad31e3850ea9d2a
Add a hdcp drm property for userspace to get hdcp encrypted
status.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I9ce516215ff51b389f2ebc72e4939e722aa1aede
clk_dp0 and clk_dp1 need enable when dp controller
enable the hdcp 2.2 function.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I9a61f187c1132b10d55bc62a3f7624705eafbca3
ksys_close depends on __close_fd which is disabled in ABI.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: I6ce61664f827699012ec16f19abb8461bb8f1acf
1. set DLL_CMDOUT_BOTH_CLK_EDGE.
2. Set RK_RXCLK_NO_INVERTER for hs200 and hs400.
3. Set the default cmd dll tap value to 05 for hs400.
4. Set strbin tap to 3 for hs400.
5. add execute_tuning api.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I911d0bbfd8e9c35cb35bd47f4b3abc1bede60c55
elan_5515 support three methods to get fwdata.
1.FROM_SYS_ETC_FIRMWARE :/vendor/etc/firmware/elants_i2c.ekt
2.FROM_SDCARD_FIRMWARE: /data/local/tmp/elants_i2c.ekt
3.FROM_DRIVER_FIRMWARE: in driver code directory *.i
choose NO.1.
Signed-off-by: Wangqiang Guo <kay.guo@rock-chips.com>
Change-Id: I9beada23a1abde4995df243f9cce9423f23ab69c
The redundant kref_get for the abort task will cause the task to fail to
free.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I8e9fa2ab75c460988c55022e15eb2f6ff55a7ada
Alternating playback of S16_LE and S32_LE audio
may cause the channel order to be reversed.
It need to clear MCLK domain logic before setting Fmclk/Fsdo.
Change-Id: I7cbfa01f5136b8815e5e2c6dc5dcda28ce49d13a
Signed-off-by: Zohn Ni <zohn.ni@rock-chips.com>
The cs inactive interrupt status is effective in both irq and dma
transmission processes.
Change-Id: I6581e8dd74f70aa1c69b888a4acae7c03351b4fd
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
1. The layout of controller registers has changed, remove legacy config;
2. Using the default value for grf register;
3. sync to use rk3568 parameter for phy PLL, signal test pass
4. Add 24MHz refclk for rk3528 PCIe, Enable the counting clock of the
rterm detect by setting tx_trim[14] bit for rx detecting.
5. set SSC modulation frequency to 31.5KHz
Change-Id: I45742c416d452037e61b7a7b8765269931d56402
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
This patch set the linestate filter time to support wakeup for
rk3528. Different from other platforms, Both the otg port and
host port have linestate_filter_con register, so we need to set
them separately.
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Change-Id: I4a78dccbdb73c48436876b72e106a2eb608ea99d
This patch add usb2 phy support for rk3528 and modified the
rk3568_vbus_detect_control as a universal interface due to
more and more platforms may use this interface in the future.
Usb2 phy also has one different design for rk3528. It doesn't
has commonon control bit, we found that there is a phy inner
debug register which can control the pll out. So we can use
this register to support phy pll control for rk3528.
Add usb2 phy tuning for rk3528:
1. Turn off differential receiver in suspend mode for
the otg and host port to save power consumption.
2. Choose the Tx fs/ls data as linestate from TX driver
for otg port which uses dwc3 controller to improve
fs/ls devices compatibility with long cable.
3. Enable both the otg and host ports phy irq to pmu
wakeup source.
4. Set HS eye-height to 400mV for rk3528
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Change-Id: Ia4a861bccd6a37db4e1ba42cede66a6b07947b5d
The cs inactive logic can always be triggered when the controller
is working, so the interrupt may be triggered when processing the
dma transmission completion interrupt.
Change-Id: I529140e43125ff3a06da67604a17afb585aafd72
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
The SPI_SR->busy is invalid for SPI slave write with ip version
ROCKCHIP_SPI_VER2_TYPE2.
Change-Id: Ib5d04a1a7859d7d47e5162f1db58f110dda8bad4
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
There are many restrictions on the use of the foresee devices Program
Load Random Data (84H), for example it's not allow after a block erase.
Change-Id: I345757016aa9b4c70b6cd5cca54f49166bb9dd99
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
VOP will triggle DMC at the following condition:
wb_en && wb_dma_finish && (vp lineflag || vp post full)
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I2ec972d74f7c8eab0088fcd96dc394e0d554020e
For compatibility with gki, dw-hdmi use callback
function instead of direct call dw-hdmi-cec wake up function.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I06fb65eadead5e3395bbd69a4dd465c95c684494
