Allow the final dts to modify the contents of rk3576.dtsi,
e.g. including rk3576-cpu-swap.dtsi
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I0802429be68d58b087979cbd992fafacb8dff76e
Allow the final dts to modify the contents of rk3576.dtsi,
e.g. including rk3576-cpu-swap.dtsi
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I2740041f036a58b2e8a44acc2d536226c6ba782a
Allow the final dts to modify the contents of rk3576.dtsi,
e.g. including rk3576-cpu-swap.dtsi
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I009a72420f50344ad9173fe9b83ac81057c3f349
Allow the final dts to modify the contents of rk3576.dtsi,
e.g. including rk3576-cpu-swap.dtsi
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ie0b70135b4e139f9912d57ef4be6b846eda1e93f
Allow the final dts to modify the contents of rk3576.dtsi,
e.g. including rk3576-cpu-swap.dtsi
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I9ce306c89653f23eb18fb32149b061883b4478c1
Allow the final dts to modify the contents of rk3576.dtsi,
e.g. including rk3576-cpu-swap.dtsi
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I7c4e3a81c9a101b9669abe875f235351bb2e0fa5
Allow the final dts to modify the contents of rk3576.dtsi,
e.g. including rk3576-cpu-swap.dtsi.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I981c1bd2541c6bb3a5fc7c1ff8126f358f85beee
BT1120 dec clk is a 4-bit integer division, which is inaccurate in
most resolutions.
For example, In bt1120->HDMI 1024x768@60Hz scenario, the actual
required clk frequency is 65MHz, while the CPLL frequency is 1188MHz.
After frequency division, the obtained frequency is 62.5MHz, which
deviates too much from the actual clk and causes the screen to be
unable to display.
So if the frequency division is not accurate, apply for a fault
tolerance of up 2% in frequency setting, so that the obtained
frequency is slightly higher than the actual required clk, so that
the deviation between the actual clk and the required clk frequency
is not significant.
Type: Fix
Redmine ID: N/A
Associated modifications: N/A
Test: N/A
Signed-off-by: Zhibin Huang <zhibin.huang@rock-chips.com>
Change-Id: Ib04c55d60211ea0cdc56a3bcc3ce49db1ceef8a8
If we want to enable regulators before system leep, just configure
property "rockchip,regulator-on-before-mem = <xx>, <xx>, <xx>..."
in rockchip-suspend node.
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: Ic421498650f0a208a070c8ceacb94f57ed897609
The dclk_delayline is to adjust the phase between dclk
and data for bt1120/bt656/rgb interface.
According to the rk3576 SI test report, the dclk_delayline
should be 0x5 in order to improve signal quality.
Change-Id: I93d3b865d0b012588ce022876af81ccc47451f32
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
According to ANDROID commit a9567a35d0 ("ANDROID: arm64: Disable workaround
for CPU errata 2441007 and 2441009"):
CPU errata 2441007 (Cortex-A55) and 2441009 (Cortex-A510) are categorised
as "rare" by Arm and consequently the workaround is not intended to be
deployed in practice as the issue is not expected to occur in real-world
environments.
Given that the cost of the workaround, which issues additional broadcast
TLB invalidation requests, has been shown to impact kswapd significantly
on Pixel devices, disable the workaround following Arm's recommendation.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I794d048a094714c1370752bfaa47bee2afd57d53
Fixes: e8ffbb71f7 ("serial: 8250: use THRE & __stop_tx also with DMA")
Change-Id: I8c30f0413a3ff7f9f36ee089ee1be5f3f4a0d045
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Remove the isr thread to reduce one thread schedule.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I4721fc6066c8580e5955f8c79025e46b96c82d85
Put "component_add" in the attach call so that dsi host and dsi device
(panel or bridge) can be regarded as a component as a whole.
dsi calls "mipi_dsi_host_register" so that the panel executes the probe
process or the bridge successfully executes "mipi_dsi_device_register_full"
during the probe process. The panel or bridge triggers "component_add"
by calling mipi_dsi_attach after the probe is successful.
Through the above modifications, you can avoid dsi defer probe infinitely
due to panel configuration errors.
Type: Fix
Redmine ID: N/A
Associated modifications: N/A
Test: N/A
Signed-off-by: Zhibin Huang <zhibin.huang@rock-chips.com>
Change-Id: Ic8782e9902a6133990fca728ab12e530e50b6d68
Use __is_defined(MODULE) to replace "#ifndef MODULE".
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I41ad334a9c4c6459bdcd0902098b16113d34c6e5
Some PCIe devices have custom power management measures that do
not rely on the PCIe framework, such as PCIe wifi, which rely on
the reset of the PCIe controller to avoid or solve potential fault
problems.
Change-Id: I7bdb0bd9edfb837a03a12790521e71adc6cd99fe
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This commit adds a new device tree source file rk3562-iotest-lp3-v10.dtsi
to describe the hardware configuration of the Rockchip RK3562 IOTEST LP3
V10 development board. It also modifies the rk3562-iotest-lp3-v10-linux.dts
and rk3562-iotest-lp3-v10.dts files to include the new
rk3562-iotest-lp3-v10.dtsi file.
The main purpose of this commit is to enable synchronized updates for
common content related to the RK3562 IOTEST LP3 V10 development board.
Change-Id: I8d5d26c12e6b4ed00b43118737f8fe36761eaab7
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
When DPTX controller config 2 pixe mode and work in sst mode,
and a low pixel clock image transmit in high link rate(HBR3),
some monitor may display flicker. To avoid this issue appear,
use lower link rate(HBR2) when transmit a low pixel clock image.
Change-Id: I75ac8fcb963631cb372dd76c4b45ca33e960f6c9
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Fixes: 7f0bc0de39 ("media: i2c: rk628: add nosignal process when get_fmt and enable stream")
Change-Id: I94b55ca0bdd9dd17168f28d25590c66e9f1dd923
Signed-off-by: Jianwei Fan <jianwei.fan@rock-chips.com>
This reverts commit 843fd2249d.
The ROPLL_SDC_N should be 1 in HBR and HBR2, which
has been confirmed with the vendor. The pervious
commit will make the SI failed to meet the specifications:
theoretical rate(Gbps) actual rate(Gbps) result
RBR 1.620 1.620 pass
HBR 2.700 2.702 fail
HBR2 5.400 5.404 fail
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I6faf6f36b43f7645739e829c761c9f61449d91a3
Cluster win1 dly num is same with win0 and saved by cluster-win0
dly_num.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Id9938a69db827513dc3000c5cb832170d0480ab4
Get phy pll freq failed in frl mode should read lcpll regs.
Fixes: fff8ec3ee9 ("phy: rockchip-samsung-hdptx-hdmi: Fix phy pll is incorrectly configured when logo is enabled.")
Change-Id: I64e973f85acd74ee251b4ab6c0a141394c116d92
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
vbus-on will trigger pmic restart when system shutdown.
Signed-off-by: Jake Wu <jake.wu@rock-chips.com>
Change-Id: I49a610f6a24c6d0ffc33a5bef7dc909f738f1f12
Fixes the following error:
ERROR: modpost: missing MODULE_LICENSE() in drivers/mfd/rkx110_x120/rkx120_pwm.o
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I27def7b919a0efcffc62f30e159066a4c21cb905
For link mode, decoder may still running after
frame ready status was written in link table.
Do soft reset before powering off the decoder
to ensure decoder is fully idle.
fixes https://redmine.rock-chips.com/issues/477479
rockchip-pm-domain 27380000.power-management:power-controller:
failed to set idle on domain 'vdec', target_idle = 1, val=0
Change-Id: I30a337bb4cd9193627ae95fae137c12d73027c38
Signed-off-by: Chandler Chen <chandler.chen@rock-chips.com>
