This reset needs to be always on, and is always on by default, so it
should not be referenced. Otherwise, once PCIe fails to enumerate the
enumerate successfully, it will be closed, which will affect other
controller that do not reference this.
Change-Id: Ie654c0c071006bd0006039286bd22acaec30df10
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
When the task is not submitted from the librga im2d API, the scale mode
may be default, so additional default configuration is required.
Change-Id: Ie5966308ad1af09a6a7eec489126670dc1085dac
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
This commit has refined the driver strength configuration of the RV1126B
from 6 levels to 23 levels
Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Change-Id: I61cee294cbb194366909acc70dec3d41a0a1e961
Delaying link training need the irq to help set dly2_done which couldn't
come true in resume due to the noirq phase. If the training is still going
but the EP issues a hot reset request, the LTSSM will be stuck and the
link never be back even if we reset the EP. The only way is to reset the
whole controller, which is unacceptable.
The issue is very difficult to be reproduced but finally we spot the key
point from fifo status of ltssm. From the designe point of view, the only
way to make ltssm from 0x0(DETECT_QUIET) to 0x5(PRE_DETECT_QUIET) is
core_rst_n be active and dly logic taking over client settings.
[816669.085768][ T2707] rk-pcie fe180000.pcie: fifo_status = 0xf0009
[816669.085775][ T2707] rk-pcie fe180000.pcie: fifo_status = 0xe000a
[816669.085783][ T2707] rk-pcie fe180000.pcie: fifo_status = 0xd000b
[816669.085790][ T2707] rk-pcie fe180000.pcie: fifo_status = 0xc000c
[816669.085797][ T2707] rk-pcie fe180000.pcie: fifo_status = 0xb0011
[816669.085804][ T2707] rk-pcie fe180000.pcie: fifo_status = 0xa000d
[816669.085811][ T2707] rk-pcie fe180000.pcie: fifo_status = 0x9000f
[816669.085818][ T2707] rk-pcie fe180000.pcie: fifo_status = 0x8000e
[816669.085826][ T2707] rk-pcie fe180000.pcie: fifo_status = 0x107000d
[816669.085833][ T2707] rk-pcie fe180000.pcie: fifo_status = 0x106000e
[816669.085840][ T2707] rk-pcie fe180000.pcie: fifo_status = 0x5000d
[816669.085847][ T2707] rk-pcie fe180000.pcie: fifo_status = 0x40005
[816669.085854][ T2707] rk-pcie fe180000.pcie: fifo_status = 0x30000
[816669.085861][ T2707] rk-pcie fe180000.pcie: fifo_status = 0x20005
[816669.085868][ T2707] rk-pcie fe180000.pcie: fifo_status = 0x10000
Given dly2_done is slef-clear bit, so we can't set it in advance but have
to disable dly2_en when linking in resume and enable it later.
Fixes: 679557456b ("PCIe: dw: rockchip: Delaying the link training after hot reset")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I85c24c7d7ea4c5f6718bcbdfbd7bf328d9a7f170
Add phy configuration of tmds clk corresponding to 10-bit color
depth at different resolutions (such as 1080p60 10-bit).
Change-Id: I8792d950dca2a51572314359044c2bea437a71a8
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Through testing, it is found that it is better to set the
DMA threshold to 64 bytes, and there will be two more interrupts
after 64 bytes without DMA, which will save time by using DMA,
but for TX, the threshold should be one byte less, because there
will be one more byte of device address.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Iebc3cd81f62d7ee8887319e121a13ed0c27984ad
Implementing JEITA charging protocols is critical for enhancing battery
safety and prolonging service life. Based on battery specifications and
operating temperatures, it is necessary to adjust charging voltages and
currents dynamically.
Change-Id: Ieab12e792697373a7b50be9e6813061ce85c1232
Signed-off-by: Shengfei Xu <xsf@rock-chips.com>
The maximum drive strength level of vccio3 is 3,
so the drive strength level configuration of DDC
SCL is 3.
Fixes: 3690970c81 ("arm64: dts: rockchip: rk3588: Adjust the HDMI DDC IO driver strength")
Change-Id: I72ed9dd669d2ef7e7fe406977d8c42e226323c99
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
