This error happens after reverting the commit,
[c3f038c2dc] "PCI: rockchip: dw_ep: Delaying the link training after hot reset"
drivers/pci/controller/dwc/pcie-dw-rockchip.c: In function 'rk_pcie_really_probe':
drivers/pci/controller/dwc/pcie-dw-rockchip.c:2105:9: error: 'struct rk_pcie' has no member named 'hot_rst_wq'
rk_pcie->hot_rst_wq = create_singlethread_workqueue("rk_pcie_hot_rst_wq");
^~
drivers/pci/controller/dwc/pcie-dw-rockchip.c:2106:14: error: 'struct rk_pcie' has no member named 'hot_rst_wq'
if (!rk_pcie->hot_rst_wq) {
^~
In file included from ./include/linux/srcu.h:21:0,
from ./include/linux/notifier.h:16,
from ./include/linux/clk.h:14,
from drivers/pci/controller/dwc/pcie-dw-rockchip.c:11:
Signed-off-by: Dongjin Kim <tobetter@gmail.com>
Change-Id: Ic948980de4a1ba9a30fbdcb4daf8f518c96f054b
This patch is to adds the panel, Elida HJ080BE31IA1, initialization
sequence and timing to ILI9881C driver.
Signed-off-by: Dongjin Kim <tobetter@gmail.com>
Change-Id: If0f06ac08c5ca4396700cfd4d950ecf493008e5f
- Create the ov5647 device tree overlays.
- Make power pin always on.
Change-Id: I00ecc943d68011167cdeaff219c89088f97a7d18
Signed-off-by: Luke go <sangch.go@gmail.com>
- Impelments features.
- test pattern.
- V4L2 stuffs
- aws, ae, auto gain.
- hflip, vflip.
- Make power enable pin always on.
- Changed color format x8 to x10.
- Add subscribe_events.
Change-Id: Ibd8d357d0c5a5e3f9d18e423fc9d93e4aecd0953
Signed-off-by: Luke go <sangch.go@gmail.com>
Support mcp2515 12M clk and 16M clk.
solved the one-bit time that came out twice as long
Signed-off-by: Steve Jeong <how2soft@gmail.com>
Signed-off-by: Dongjin Kim <tobetter@gmail.com>
Change-Id: I47a405f11cdf290deacb9fa266d31525d80cacfc
change can0 clock freq 150MHz to 200MHz
to make the signal more stable.
Signed-off-by: Steve Jeong <how2soft@gmail.com>
Change-Id: Icab5a5fd350537e9e9f80c13b6e92925a598c86f
for change i2c bus freq dynamically.
e.g.
$ echo 400000 | sudo tee /sys/bus/i2c/devices/i2c-0/device/speed
Signed-off-by: Steve Jeong <how2soft@gmail.com>
Change-Id: Ifcccf9bb61ed65133b64c803b53fb4e46d470e26
Comes with the first DTBO file, fanspeed-full.dts
Signed-off-by: Steve Jeong <how2soft@gmail.com>
Signed-off-by: Deokgyu Yang <secugyu@gmail.com>
Change-Id: I1e3c18d026b1ebdd9d80a7b23b383b15d568fc42
Signed-off-by: Dongjin Kim <tobetter@gmail.com>
Signed-off-by: Deokgyu Yang <secugyu@gmail.com>
Signed-off-by: Steve Jeong <how2soft@gmail.com>
Change-Id: Ifbcc33e8e5c3064b3f4cbd3f6a92224346c4f4b3
ODROID-M1: arm64/dts: change i2c2 pinctrl.
- Changed the I2C-2 default pinctrl to i2c2m1_xfer.
Signed-off-by: Luke Go <sangch.go@gmail.com>
Change-Id: Id234f0d73100e98502b86f91b455cacc2fc6847f
On the RK3562 SoC, the HPLL is designed dedicated for audio.
This patch assigns PLL_HPLL as the parent of digital audio
interface default. and Set PLL_HPLL to 983.04M(48k group)
default to achieve better jitter performance.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I21615ae46209a2be31630987350131abd3b33a97
Currently, the BCLK/FSYNC enable is addressed in hw_params
stage, because the real clk is measured by samplerate. so,
it is quite a good solution.
But, on the system PM situation, it is failed to recovery
BCLK/LRCK after resume. the root cause is that never do
'hw_params' after resume. which is similar to XRUN issue.
So, let's move it to prepare stage which any path must do
before trigger-start.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I9025a98259a4e9bd9f09ec3d23584f753552031d
This patch use the generic pm_runtime_force_* API for system PM,
because both of them do the same action. let's make it implemented
with runtime PM.
Ref: commit 37f204164d ("PM: Add pm_runtime_suspend|resume_force functions")
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ice5057ca5cdf8999990283a99921b7b6a30cd557
1. NV12/NV16/YUYV xoffset must aligned as 2 pixel;
2. NV12/NV15 yoffset must aligned as 2 pixel;
3. NV30 xoffset must aligned as 4 pixel;
4. NV15/NV20 xoffset must aligend as 8 pixel at rk3568/rk3588/rk3528/rk3562,
others must aligned as 4 pixel;
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I28d69d1f8189963170ef798c12bfd60fb092ef20
