This driver is modified to support RK3528 SoCs.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: If024916eb7b52ec86ff7533aedefc1bda457b612
According to a description from TRM, add all the idle request.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I3c58c73a61bf88d91930f9f3464207f820965b94
Add the clock tree definition for the new RK3528 SoC.
gmac1 clocks are all controlled by GRF, but CRU helps to abstract
these two clocks for gmac1 since the clock source is from CRU.
The io-in clocks are module phy output clock, gating child
clocks by disabling phy output but not CRU gate.
Add gmac0 clocks.
They are all orphans if clk_gmac0_io_i is not registered by
GMAC driver. But it's fine that GMAC driver only get it but
not to set/get rate.
Add CLK_SET_RATE_PARENT for mclk_sai_i2s0/1.
Allowed to change parent rate.
Add CLK_SET_RATE_NO_REPARENT for dclk_vop0.
dclk_vop0 is often used for HDMI, it prefers parent clock from
clk_hdmiphy_pixel_io for better clock quality and any rate.
It assigns clk_hdmiphy_pixel_io as parent in dts and hope not to
change parent any more.
Add CLK_SET_RATE_PARENT for aclk_gpu.
Allow aclk_gpu and aclk_gpu_mali to change parent rate.
Add CLK_SET_RATE_PARENT for aclk_rkvdec_pvtmux_root.
Allow aclk_rkvdec_pvtmux_root and aclk_rkvdec to change parent rate.
set aclk_m_core = core_clk/2.
aclk_m_core signoff is 550M, but we set div=2 for better
performance.
Add CLK_IS_CRITICAL for clk_32k.
Mainly for pvtpll during reboot stage.
Add CLK_IS_CRITICAL for all IOC clocks.
IOC doesn't share clock with GRF. The iomux can't be changed if they
are disabled.
Disable aclk_{vpu,vpu_l,vo}_root rate change
They are all shared by multiple modules, disable rate change
by modules.
Don't register clk_uart_jtag
It's for force jtag uart delay counter. It must be open
for box product without tf card but with uart0.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I09745b6a31484d6a27f04e608268d9738c1fe224
Add the dt-bindings header for the rk3528, that gets shared between
the clock controller and the clock references in the dts.
Add softreset ID for rk3528.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I465f0a3c7fc36eee4c2ab0de38a810b8e691d41e
clk init is only used at rk3588 but rk3528 version is bigger
then rk3588
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I0730242f223b6ab3b48765c13fe4ff1ab2803570
Add branch_gate_no_set_rate for gate clks not
allowed to support setting rate.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Ic940acbc035804a011e59b8e1a0d440168e18c26
fix suspend error by vir dev and hw dev run SYSTEM_SLEEP_PM_OPS
Change-Id: I10971c3f43debf082278cf13aacf68eb97d2f0c3
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
1、Fixes brightness is increasing to a stable value when
sensor’s exp reg is fixed value
2、Fixes cross stripe in the first 15 frame
this patch will delay 3ms before frame start
Signed-off-by: Su Yuefu <yuefu.su@rock-chips.com>
Change-Id: I40ea052ae9e4677b5dc0451ce683f5445feeeed5
BACKGROUND:
DTS-HD Bitstream sounds noise occasionally on Denon-AVR-X2700H,
and we found this happen sometime on PLL(frac mode), But it's gone
on PLL(int mode).
This patch Assign parent of I2S5/6 which used for HDMI0/1 to GPLL
to fix DTS-HD Bitstream noise occasionally on Denon-AVR-X2700H.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I071409278ab983af3c32e7b282de1e2819bb706b
BACKGROUND:
DTS-HD Bitstream sounds noise occasionally on Denon-AVR-X2700H,
and we found this happen sometime on PLL(frac mode), But it's gone
on PLL(int mode).
This patch Adds "CLK_SET_RATE_NO_REPARENT" for I2S5/6 which used
for HDMI0/1 to make its parent fixed from GPLL(int mode) to fix
DTS-HD Bitstream noise occasionally on Denon-AVR-X2700H.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I5694c0a7839df817fd32b82ce69450f0eebdcf77
The dwc2 driver use the nak interrupt for the starting point
of isoc-in transfer. The first nak interrupt for isoc-in means
that in token has arrived and the dwc2 driver can obtain the
(micro) frame of the token to set the even/odd (micro) frame
field of DIEPCTL.
However, on some platforms (e.g Rockchip rk3308) which don't
support the "OTG_MULTI_PROC_INTRPT", it means that all device
endpoints share the same nak mask and interrupt. If the nak
interrupt is always enabled, it may trigger nak interrupt storm
by other endpoints except the isoc-in endpoint. So we disable
the nak interrupt when get first isoc in token if the feature
"OTG_MULTI_PROC_INTRPT" isn't enabled.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I99c71a5e0d7903346fd8f71619b6736c3181c0ec
Because struct rga_external_buffer is not initialized before importbuffer.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: I51e341b80aee6bb4ea70eee4f6c9a247947a8f85
