There are two copies of the same power management code
in rk_rng_v1_read and rk_rng_v2_read, moved to rk_rng_read.
Change-Id: I104cf22a8093213a6d22f7a723d3cfaf36aa4414
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
rng module should use scmi_clk rather than cru.
Fixes: b56b10f007 ("arm64: dts: rockchip: rk3588s: add rng node")
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: I49994529fcc209c2bc173c1abc497536fb920302
The software utilizes I_COMP and I_BC_LVL interrupts to determine an
attach and what type of port is attached. and I_COMP interrupt also
alerts software that a SRC detach has occurred. So unmask I_COMP for
SRC and I_BC_LVL for SNK.
Fixes: 48242e3053 ("usb: typec: fusb302: Revert "Resolve fixed power role contract setup")
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: Ib4cf3b752d0db116f2603d5e1f3ee5c7d114714a
All the digital-fracdiv signoff freq are the same, and up
to 1.5G on rk3588.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Id4b6b43c05b256a2b77d3c6c0603953b7340eca0
As we mask our SDHCI controller as SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
host->max_clk is derived from core clock in the first place. Then
f_max works together with it.
If we adjust loader's core clk setting, such as 50MHz, we will get
50MHz for host->max_clk, because .get_max_clock() reads core clk
when probing driver. That will lead f_max be set to 50MHz as well,
no matter if max-frequency is set higher than 50MHz.
We can simple solve this problem by assigning core clk as 200MHz
in the first place and then let max-frequency property takes over
it.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I25986720fa441da3786ca0904a2d4b1a5b0568e5
1. set CARD_IS_EMMC bit to enable Data Strobe for HS400
2. config the transmit clock source (DLL TX) is original clock input
3. config Command output source and Command output enable are from
register output triggered by clock falling edge
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I5b34fecde7bb1d05211c7d9c42f54c8e154d367e
Picked from ./platform/devicetree/.
This makes GPU utilisation info available and resolve the warning log below:
[ 19.641700][ T83] WARNING: CPU: 0 PID: 83 at drivers/gpu/arm/bifrost/csf/ipa_control/mali_kbase_csf_ipa_control.c:239 kbase_ipa_control_handle_gpu_power_off+0x128/0x198
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
Change-Id: I7ce8d0f52d6340659b2c9ca9692c48043e1060c1
Enable the DP driver used on Rockchip RK3588 SoC.
Signed-off-by: Huang zhibao <hzb@rock-chips.com>
Change-Id: I4d645edebf90ceaa35b52b0ccf029c17d1a51e67
To use tsadc_shut function, tsadc must switch to cru_shut_mode,
because tsadc_shut signal have to go through the cru to get to
tsadc_shut signal.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I9bc816db35bdf1c107db4e301d9f3353cb651dcf
rk3588 boards may have different pcie3-phymode, default as below id not
set:
rockchip,pcie30-phymode = <PHY_MODE_PCIE_AGGREGATION>;
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: If158eb47f679d0c7b184b6bd64262d0f764b97f3
rk3588 boards may have different pcie3-phymode.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I76825c09014481a06af4c04d0b9b1cc0fee89a8d
Restore usbotg0 dr_mode to "otg" that Type-C controller can switch the
mode via "role_switch" callback for RK3588 EVB1, EVB3 and EVB4.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I6e7d83acb468d50e31ffdfdee6adcd7c5330d776
use helper functions to send dsi picture parameter set data
type packets, the size of struct drm_dsc_picture_parameter_set
is 128 bytes, it may be greater than the size of pps panel required,
so the redundant part should default to zero.
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I8b937b052cc0d579dd78859ef1aa04aea818d694
drivers/gpu/drm/rockchip/dw-dp.c:1911 dw_dp_audio_infoframe_send()
error: hdmi_audio_infoframe_pack() '&buffer[4]' too small (26 vs 30)
Fixes: 9548fbb10c ("drm/rockchip: Add support for Synopsys DesignWare Cores DPTX")
Change-Id: I34142ae76b428c4ada3debfe80698af63ffd8f1f
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Some vendor drivers rely on flow control by toggling
enable/disable virtual irq if using legacy interrupt.
It can certainly change the behaviour by function
drivers, but adding corresponding operations would make
RC driver more flexible.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Idf3e6a0ca9c4ebde369745713a88db53e3f72ea5
Add a new driver for Synopsys DesignWare Cores DPTX IP used
in Rockchip RK3588 SoC. The DPTX is compliant with the
DisplayPort Specification Version 1.4.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I0588aae8b3c9ae19ab7ee5d2c86673aa35cee2ff
Enable the DP driver used on Rockchip RK3588 SoC.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I9b6c817746c74bc3f50df302dfbdae1e80324fb8
in order to switch dsi2 working mode, operation DSI2_PWR_UP from
power on to power off and then power on, it may trigger dsi2 host
to send unexpected cmd to panel, resulting in panel abnormality,
therefore, do not operate DSI2_PWR_UP when switching the working
mode.
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I78d969dbc16262c9f7367fe5c25688d84cb1f935
1 rk3588_udphy_cfgs is used to define const data, remove
dp lane map grf register from it;
2 fix the dp lane mapping mismatch issue.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I3c179596c0c9c961afb0f0ee46a3b5f0f01d23a1
In usbdp-phy, the DP function can use all or only part of
the phy lanes. This info need notify DP controller.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Ib943532d7a764602392837f9a9163af00e8e7918
When enter DP mode, exit DP mode, disconnect device, the data
is NULL. And only check the hpd is connect, set the gpio.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I7a3558c5ee5f954055fdd5edbbd50b5079d8f323
According the dp lane mapping, set the swing and pre-emphasis
to phy lane.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I77bec31a8a7b026db7e799991157114273ab0d4c
rk3588 has 2 usbdp phy, usbdp phy use aliased id to identify
the 2 usbdp phy devices.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I59c634eb2c74ac48bbf067883c6ed12fd0e3e5eb
+CONFIG_WL_ROCKCHIP=y
+CONFIG_WIFI_BUILD_MODULE=y
+CONFIG_AP6XXX=m
+CONFIG_BCMDHD_PCIE=y
-# CONFIG_NET_VENDOR_REALTEK is not set
+CONFIG_R8168=y
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: Icb986d4e419054beb5bb271f37f965e9120348ce
