1.vepu aclk is ACLK_H264 and hclk is HCLK_H264
2.vepu need clk_core clk define
3.add h264&h265 power domain
Change-Id: I419e544cf86d90b2b8d88dd13dfed49d31a24991
Signed-off-by: Xinhuang Li <buluess.li@rock-chips.com>
add gpu as a cooling device in thermal control
Change-Id: Ia9db5df7b2d5d9ed19672f64f8924877016732c2
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
support rk3328 cvbs.Some display parameter can be configured,
such as saturation.For more information, please check
Documentation/devicetree/bindings/display/rockchip/rockchip_drm_tve.txt
Change-Id: Ifcc074a34910b58a26fc309fc601494562851025
Signed-off-by: algea.cao <algea.cao@rock-chips.com>
This commit would enable the VDPU and RKVDEC devices.
The VDPU works in the non combo mode.
Change-Id: I643350d5a2ac17759984fda2e95fb2b82701e7cf
Signed-off-by: Randy Li <randy.li@rock-chips.com>
Jung and I meet some problem the video decoder, so
we just release the VDPU standalone this time.
It seems that the iommu can't attach to two different
IP at the same time.
Change-Id: I24d73cd5ab2c3d32da6ef29661061c7fda9186f2
Signed-off-by: Randy Li <randy.li@rock-chips.com>
rk3328 dwc3 has a problem that USB 2.0 MAC lineState not
reflect the expected line state (J) during transmission.
Add this quirk to add the ipgap between (tkn to tkn/data)
with 40 bit times of TXENDDELAY, and linestate is ignored
during this 40 bit times delay.
Change-Id: I76895476bff94c2198a5d8df7e73b9d54fbb96ed
Signed-off-by: William Wu <william.wu@rock-chips.com>
The USB 3.0 PHY need to config grf when change between
USB 2.0 only and USB 2.0/3.0 mode, so we add grf property
for u3phy node.
Change-Id: I4ff2670d0637e9d0cbae06f5e9efbde9a8513bb3
Signed-off-by: William Wu <wulf@rock-chips.com>
This patch adds a quirk to disable rk3328 xHCI controller
USB3 port autosuspend function, and USB2 port autosuspend
function is still enabled.
Change-Id: Ie5e6883811b09a9a0d839ce59d8f9c4ad8ad3378
Signed-off-by: William Wu <wulf@rock-chips.com>
This patch adds USB 3.0 PHY grf node and apb node
for rk3328 USB 3.0 module.
Change-Id: I9d4e6c6d6792ac5fd6c2a4d7cc902f1ff0cf4ef1
Signed-off-by: William Wu <wulf@rock-chips.com>
This patch doesn't fix any issue, but conforms
to linux coding style.
Change-Id: I87326a21594b905ea5791f73efc1cea0299abe4d
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Rk3399 support single and burst mode, and flushp instruction.
But burst mode improve transfer efficiency.
Please refer to:
Commit 8e770f371c
"dmaengine: pl330: add burst mode according to dts config"
Change-Id: I2eb36723697cf548dc75aca0e5a276a86cd2419d
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
set armclkb 816M to slove the crash,which reset core voltage below 0.85V.
So make sure the 0.8V voltage is enough for the init clk freq.
Change-Id: I4dba25fdfd610c0751f50ce09283c32a9b3f420f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Rockchip RK3399 SoCs support reboot with modes, such as recovery mode,
loader mode and normal mode.
Change-Id: I96ed872f849c2b3b06d236248995db18be070960
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Let's assign clk parent and rate for SCLK_EMMC to meet the
requiremen.
Change-Id: I3730a2124494da51717b1756f488f9df5bcd6423
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
