Commit Graph

1061086 Commits

Author SHA1 Message Date
Sia Jee Heng
a916d4e8d3 UPSTREAM: ASoC: codec: hdmi-codec: Support IEC958 encoded PCM format
Existing hdmi-codec driver only support standard pcm format.
Support of IEC958 encoded format pass from ALSA IEC958 plugin is needed
so that the IEC958 encoded data can be streamed to the HDMI chip.

Change-Id: I01516e34605e380995b5312273035a0d000d36f1
Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
Link: https://lore.kernel.org/r/20210204014258.10197-2-jee.heng.sia@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
(cherry picked from commit 28785f548d)
2021-11-24 11:08:24 +08:00
Stephan Gerhold
71e6844b4a UPSTREAM: ASoC: hdmi-codec: Fix return value in hdmi_codec_set_jack()
Sound is broken on the DragonBoard 410c (apq8016_sbc) since 5.10:

  hdmi-audio-codec hdmi-audio-codec.1.auto: ASoC: error at snd_soc_component_set_jack on hdmi-audio-codec.1.auto: -95
  qcom-apq8016-sbc 7702000.sound: Failed to set jack: -95
  ADV7533: ASoC: error at snd_soc_link_init on ADV7533: -95
  hdmi-audio-codec hdmi-audio-codec.1.auto: ASoC: error at snd_soc_component_set_jack on hdmi-audio-codec.1.auto: -95
  qcom-apq8016-sbc: probe of 7702000.sound failed with error -95

This happens because apq8016_sbc calls snd_soc_component_set_jack() on
all codec DAIs and attempts to ignore failures with return code -ENOTSUPP.
-ENOTSUPP is also excluded from error logging in soc_component_ret().

However, hdmi_codec_set_jack() returns -E*OP*NOTSUPP if jack detection
is not supported, which is not handled in apq8016_sbc and soc_component_ret().
Make it return -ENOTSUPP instead to fix sound and silence the errors.

Cc: Cheng-Yi Chiang <cychiang@chromium.org>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Fixes: 55c5cc63ab ("ASoC: hdmi-codec: Use set_jack ops to set jack")
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Acked-by: Nicolin Chen <nicoleotsuka@gmail.com>
Link: https://lore.kernel.org/r/20210107165131.2535-1-stephan@gerhold.net
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 2a0435df96)

Change-Id: Id38ce1cdfc80daaac7d77212cecd29dd6fa4e877
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2021-11-24 11:08:24 +08:00
Shengjiu Wang
57f647c6cb UPSTREAM: ASoC: hdmi-codec: Add RX support
HDMI interface can also be used as receiver, this patch is to
add such support. The most difference compare with TX is that RX
don't need to get edid information.

Change-Id: Ib5f9f347cd50abe95fa9c8a4856bd1a91117ca67
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link: https://lore.kernel.org/r/1606372608-2329-1-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
(cherry picked from commit 144f836646)
2021-11-24 11:08:24 +08:00
Cheng-Yi Chiang
cf648c7c0f UPSTREAM: ASoC: hdmi-codec: Get ELD in before reporting plugged event
In plugged callback, ELD should be updated from display driver so that
user space can query information from ELD immediately after receiving jack
plugged event.

When jack is unplugged, clear ELD buffer so that user space does not get
obsolete information of unplugged HDMI.

Change-Id: I2245de6e6f7dbc64863267db864dafdd3af95747
Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
Link: https://lore.kernel.org/r/20201118043852.1338877-1-cychiang@chromium.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
(cherry picked from commit 25ce4f2b35)
2021-11-24 11:08:24 +08:00
Tao Huang
8d6989ba85 MALI: bifrost: Fix -Wmissing-prototypes warnings
drivers/gpu/arm/bifrost/mali_kbase_core_linux.c:2955:6: warning: no previous prototype for function 'kbasep_ktrace_dump_wrapper' [-Wmissing-prototypes]
drivers/gpu/arm/bifrost/backend/gpu/mali_kbase_irq_linux.c:182:13: warning: no previous prototype for function 'kbase_gpu_irq_test_handler' [-Wmissing-prototypes]
drivers/gpu/arm/bifrost/backend/gpu/mali_kbase_irq_linux.c:210:5: warning: no previous prototype for function 'kbase_set_custom_irq_handler' [-Wmissing-prototypes]
drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c:241:5: warning: no previous prototype for function 'rk_kbase_device_runtime_init' [-Wmissing-prototypes]
drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c:246:6: warning: no previous prototype for function 'rk_kbase_device_runtime_disable' [-Wmissing-prototypes]
drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c:266:5: warning: no previous prototype for function 'kbase_platform_early_init' [-Wmissing-prototypes]
drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c:274:6: warning: no previous prototype for function 'kbase_platform_rk_shutdown' [-Wmissing-prototypes]
drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c:460:5: warning: no previous prototype for function 'kbase_platform_rk_init_opp_table' [-Wmissing-prototypes]
drivers/gpu/arm/bifrost/ipa/mali_kbase_ipa.c:399:5: warning: no previous prototype for function 'kbase_scale_static_power' [-Wmissing-prototypes]

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I47be45c9ac2b7f9eedec1977d358b535f7fbd795
2021-11-24 09:53:51 +08:00
Jianwei Fan
fbed03a602 ARM64: rockchip_defconfig: enable CONFIG_VIDEO_OV13855
enable ov13855 camera driver used for rk3588s-tablet

Signed-off-by: Jianwei Fan <jianwei.fan@rock-chips.com>
Change-Id: Idd3b50b20fc451c18f57eac337ac58c219f957e4
2021-11-23 21:16:14 +08:00
Jianwei Fan
3844ce0ba5 media: i2c: ov13855: add camera driver ov13855
Signed-off-by: Jianwei Fan <jianwei.fan@rock-chips.com>
Change-Id: I72723e34c7712093bd6fa639528177d5d14bc5b8
2021-11-23 21:15:59 +08:00
Wyon Bi
3fdf77eb6f drm/rockchip: vop2: Add pclk support
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: If35f3ce459a9e36df562fa015e47d2ecf2d740d2
2021-11-23 20:59:23 +08:00
Wyon Bi
01ac874b5c arm64: dts: rockchip: rk3588s: Add pclk to vop node
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: If8b8ed6760e90e9dfd8f739ccfd5a79b928d10c1
2021-11-23 20:59:23 +08:00
Wyon Bi
9c9db5fd41 clk: rockchip: rk3588: export pclk_vopgrf id for vop
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I1d1d2b8d0a87763f1671ce0bc6f9933caaac3800
2021-11-23 20:59:23 +08:00
Wyon Bi
cd17a24cbd arm64: dts: rockchip: rk3588: Add hclk to dp node
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Icd10a683360834d7326a22b37ee648626dc02883
2021-11-23 20:59:22 +08:00
Wyon Bi
7a66a44e9e arm64: dts: rockchip: rk3588: Add hclk to edp node
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ibe702f41c0a3a585cd20a22856bf1065dc842a03
2021-11-23 20:59:22 +08:00
Wyon Bi
487451ecd3 arm64: dts: rockchip: rk3588: Fix clock-cells for link clocks
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Icd39f13b53546407b4a850eace46aaba3ab3d7b7
2021-11-23 20:59:22 +08:00
Wyon Bi
e0a703613d clk: rockchip: link: Add of clk provider support
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I8318ea3a6e582043f0f1f668502f76b063e9719b
2021-11-23 20:59:22 +08:00
William Wu
a038f27bf1 arm64: dts: rockchip: rk3588: Add phy utmi clk for usb2 host
This patch add UTMI clk from usb2 phy for usb2 host controllers.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I4f7f297ffb09aa1a9d81e625c67933883d98588d
2021-11-23 20:56:25 +08:00
William Wu
212a44da74 arm64: dts: rockchip: rk3588-evb: remove hs limit for usb3_0
Because the usb3_0 super-speed driver is ready, let
remove the maximum-speed limit.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Iebe2ebdeddb2942f6bb333b2bedf31f7f3c02557
2021-11-23 19:47:31 +08:00
William Wu
9e3a19c70f arm64: dts: rockchip: rk3588: Add u2 and u3 phys for usb controllers
This patch adds usb2_phy0 and usbdp_phy0 for usb3_0 otg,
usb2_phy1 and usbdp_phy1 for usb3_1 otg, usb2_phy2 for
usb2_0 host, usb2_phy3 for usb2_1 host.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I10eff4d7e993c317517f9cf86f6d126238c53f4e
2021-11-23 19:46:29 +08:00
Frank Wang
ee3ec96219 phy: rockchip: usbdp: amend to support u3
Add below changes to support U3:
 - amend registers of the init sequence.
 - amend 24MHz refclk registers and add 26MHz refclk support.
 - add maximum-speed property for USB.
 - cleanup codes and add fault-tolerant process.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I25ca3cb8c81a36691200277d94ac0a21bc9b57cb
2021-11-23 19:44:25 +08:00
William Wu
0221f1547f phy: rockchip: inno-usb2: Add usb2 phy support for rk3588
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I71c3ae35a67eba0157538f9c0980a7cc4b767727
2021-11-23 19:44:25 +08:00
William Wu
8dae8f2c0d phy: rockchip: inno-usb2: fix charge detection
Fixes: 61b9414d71 ("phy: rockchip: inno-usb2: keep utmi clk on during charge detection")
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Ifcaf0ec333399a73a0c7af32cc053379763b83c2
2021-11-23 19:44:25 +08:00
William Wu
4450c2a62e dt-bindings: phy: rockchip-inno-usb2: add binding for rk3588 usb2 phy
This adds "rockchip,rk3588-usb2phy" compatible property.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I916040169de3a7dff3440c9b4c8e4c141e2ddc72
2021-11-23 19:40:00 +08:00
William Wu
e965947374 arm64: dts: rockchip: rk3588: disable receiver detection in P3 for usb3 host
RK3588 USB3_2 Host controller require to disable receiver detection
in P3 for correct detection of USB devices. Add this quirk to set
the GUSB3PIPECTL.DISRXDETINP3, then the DWC3 core will change the
PHY power state to P2 and then perform receiver detection. After
receiver detection, the DWC3 core will change the PHY power state
to P3 state.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I4043e022e839c9ebe669d7cb9962448916d928a8
2021-11-23 19:39:50 +08:00
Andy Yan
c592de017c drm/rockchip: vop2: Both dsp_background of two Video Ports should be set in splice mode
Both dsp_background of two Video Ports should be set in splice mode

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: Idc8cee79bd590cc944e553e2081cef526b5ea466
2021-11-23 19:24:13 +08:00
Andy Yan
49f21efd68 drm/rockchip: vop2: Fix dly in splice mode
The right VP share the same display timing
with left VP.

We must make sure the PRE_SCAN_TIMING of
right VP is configured in splice mode.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I0af0cbdf18580aa1bb8bfe48210278dc61c14fcd
2021-11-23 19:24:13 +08:00
Andy Yan
bf6b922146 drm/rockchip: vop2: Skip disable right splice win if only display on the right screen
We have a case only use right window(a plane display on right part of
the screen) in splice mode, so we need to only disable the left window
by ourself, but enable the right window.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: Iab4ad7b88e89c989eae521faefe2b700a18d913c
2021-11-23 19:24:13 +08:00
Andy Yan
fa631748f8 drm/rockchip: vop2: Disable right VP and win in splice mode
The VP(CRTC) and WIN(plane) of right part is invisible for
userspace.

We should disable it when the userspace want to disable
the left part VP and Plane.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I9fa0385e345a699bc13df9b6b65f4f26c5538200
2021-11-23 19:24:13 +08:00
Andy Yan
5e083cfd18 drm/rockchip: vop2: Fix left dsp_w in splice mode
Fix the left dsp_w calculation

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: Ibdb58e689dcaf6e6571dd9fcb8f3ef2fe9d74ece
2021-11-23 19:24:13 +08:00
Andy Yan
d11cdd20db drm/rockchip: vop2: Set splice win in plane_atomic_check
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I975cfd1b11228257b8b5a2b5d4c38ec79891dce4
2021-11-23 19:24:13 +08:00
Andy Yan
b8e518de04 drm/rockchip: vop2: Add XRGB2101010 support
This format is AFBC only, line mode is not supported.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: Id7d6449cbdfbc44a3d10e8df8fba511cc3c4f557
2021-11-23 19:24:13 +08:00
Finley Xiao
4060d28594 arm64: dts: rockchip: rk3588-evb: Add supply regulators for gpu
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I8d71a14054c2340b6ee6044b12472cfaea2d8081
2021-11-23 17:24:11 +08:00
Jianhui Wang
c87b8fcb8a arm64: dts: rockchip: rk3588s-tablet: add dp display for rk3588s tablet
Signed-off-by: Jianhui Wang <wjh@rock-chips.com>
Change-Id: I706d737fff06724d46ed56675d1dc620f10dbb27
2021-11-23 16:55:25 +08:00
Shunhua Lan
02959a1d28 arm64: dts: rockchip: rk3588s-tablet: add es7202 mic array
Change-Id: I7e5b76bc10fe8321788135de9f45298fa73b00ad
Signed-off-by: Shunhua Lan <lsh@rock-chips.com>
2021-11-23 16:44:11 +08:00
Finley Xiao
98a9b2cbb4 MALI: bifrost: Add memory regulator support
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I95d3ceccc5cd14caefb96c1c3266d7b4d8520719
2021-11-23 16:34:03 +08:00
Caesar Wang
2084b9f118 MALI: bifrost: fixes wrong number of regulators
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: Icb1e4a388e6e8720036b6a1d85a13b5e2491cf4d
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
2021-11-23 16:32:28 +08:00
Sugar Zhang
7785ff2166 arm64: dts: rockchip: rk3588: Assign clk parent for DAIs
This patch assigns PLL_AUPLL as the parent of digital audio
interface default.

Except for:
 I2S1_8CH which is fixed bind to PLL_CPLL
 PDM0 which is fixed 300M/200M from PLL_GPLL/CPLL.

And Set PLL_AUPLL to 786.432M(48k group) default to achieve
better jitter performance.

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I1f06a7a37691803b41768ac329917912c377a9e7
2021-11-23 15:37:15 +08:00
Sugar Zhang
f9bd0486a1 clk: rockchip: rk3588: Add audio fracpll freq
This patch adds more audio fracpll freq around 800M.

786432000 for SR:
  8k, 16k, 24k, 48k, 96k, 192k

722534400 for SR:
  11.025k 22.05k, 44.1k, 88.2k, 176.4k

According to CRU Chapter:

+------------+---------------------------------------------------------+
| PLL Type   | Equation                                                |
+------------+---------------------------------------------------------+
| FRACPLL    | FFVCO = ((m + k / 65536) * FFIN) / p                    |
|            | FFOUT = FFVCO / 2^s                                     |
+------------+---------------------------------------------------------+

e.g. to achieve PLL rate: 786432000

step1:

equation: FFVCO = FFOUT * 2^s to get VCO as much higher as possible in
ranges for better jitter performance.

FFVCO = 786432000 * 2^2 = 3145728000

step2:

equation: ref = FFIN / P, (m + k / 65536) = FFVCO / ref
ref should be as much higher as possible for better jitter performance.

we can try to iterate from high freq to low to find the best parameter.

step3:

the final FFOUT should be measured by devices, sush as frequency
counter.

RK3588_PLL_RATE(786432000, 2, 262, 2, 9437)
RK3588_PLL_RATE(722534400, 8, 963, 2, 24850)

+------------------------------------------------------------------------+
| MHz  | 1~63 | 64~1024 | 0~6 | 0~65535 |     |  2250~4500  |  36~4500   |
+------------------------------------------------------------------------+
| FFIN |  p   |    m    |  s  |    k    | ref |    FFVCO    |   FFOUT    |
+------------------------------------------------------------------------+
| 24   |  2   |   262   |  2  |   9437  | 12  | 3145.727993 | 786.431998 |
+------------------------------------------------------------------------+
| 24   |  8   |   963   |  2  |  24850  |  3  | 2890.137560 | 722.534390 |
+------------------------------------------------------------------------+

Target freq measured by KEYSIGHT-53220A (Universal Frequency Counter)

+------------+---------------------+---------------------+-------------+
| PLL (MHz)  | Freq required (MHz) | Freq measured (MHz) | Delta (ppm) |
+------------+---------------------+---------------------+-------------+
| 786.432000 | 49.152000           | 49.151360           | 13          |
+------------+---------------------+---------------------+-------------+
| 786.432000 | 12.288000           | 12.287841           | 13          |
+------------+---------------------+---------------------+-------------+
| 722.534400 | 45.158400           | 45.157816           | 13          |
+------------+---------------------+---------------------+-------------+
| 722.534400 | 11.289600           | 11.289453           | 13          |
+------------+---------------------+---------------------+-------------+

And this patch also fix freq for 983.04M and 903.168M.

Before:

RK3588_PLL_RATE(983040000, 3, 491, 2, 34078)
RK3588_PLL_RATE(903168000, 3, 451, 2, 38272)

+------------+---------------------+---------------------+-------------+
| PLL (MHz)  | Freq required (MHz) | Freq measured (MHz) | Delta (ppm) |
+------------+---------------------+---------------------+-------------+
| 983.040000 | 49.152000           | 49.051368           | 2047        |
+------------+---------------------+---------------------+-------------+
| 983.040000 | 12.288000           | 12.262841           | 2047        |
+------------+---------------------+---------------------+-------------+
| 903.168000 | 45.158400           | 45.057819           | 2227        |
+------------+---------------------+---------------------+-------------+
| 903.168000 | 11.289600           | 11.264454           | 2227        |
+------------+---------------------+---------------------+-------------+

After:

RK3588_PLL_RATE(983040000, 4, 655, 2, 23592)
RK3588_PLL_RATE(903168000, 6, 903, 2, 11009)

+------------+---------------------+---------------------+-------------+
| PLL (MHz)  | Freq required (MHz) | Freq measured (MHz) | Delta (ppm) |
+------------+---------------------+---------------------+-------------+
| 983.040000 | 49.152000           | 49.151367           | 13          |
+------------+---------------------+---------------------+-------------+
| 983.040000 | 12.288000           | 12.287841           | 13          |
+------------+---------------------+---------------------+-------------+
| 903.168000 | 45.158400           | 45.157818           | 13          |
+------------+---------------------+---------------------+-------------+
| 903.168000 | 11.289600           | 11.289454           | 13          |
+------------+---------------------+---------------------+-------------+

Fixes: 72c304699f ("clk: rockchip: rk3588: Add audio fracpll freq")

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Iacc74d135efacef5b6b65d30bdf235ceec0fe970
2021-11-23 15:37:09 +08:00
Shunhua Lan
267e9b4290 ASoC: es7202: add supply voltage recognizing and set channels_max to 8
Signed-off-by: Shunhua Lan <lsh@rock-chips.com>
Change-Id: Icda031758b217c1b7c3524d6fe9ffd6a542f8bcf
2021-11-23 15:15:08 +08:00
Sandy Huang
0e6433e98f drm/rockchip: vop2: add support RGB101010 and update dither config
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I616225d36ff3a7385c5937fc663ff063f0683b0c
2021-11-23 15:10:27 +08:00
Elaine Zhang
cb1f0723c1 clk: rockchip: rk3588: use COMPOSITE_DCLK for dclk_vp2
div = DIV_ROUND_UP_ULL(400000000, rate);

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I6106b9e661db21392af3185c4d3a1f17cd5d844f
2021-11-23 11:20:24 +08:00
shengfei Xu
7534ec9a51 arm64: dts: rockchip: rk806: bind the rk806 to the rk3588
rename "rk806-double.dtsi" to "rk3588-rk806-daul.dtsi"
rename "rk806-single.dtsi" to "rk3588-rk806-single.dtsi"

Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I0f2de1d32a0cd2ed6d551dca7cdf7ebb6eb6d990
2021-11-23 11:09:30 +08:00
Tao Huang
bb61e2f640 arm64: rockchip_gki.config: Enable CONFIG_SND_SOC_ROCKCHIP_HDMI
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ifabffd2a06c9ba94766dc7c6f236b395c0754323
2021-11-23 10:44:59 +08:00
XiaoTan Luo
7579511593 arm64: configs: rockchip_defconfig: enable SND_SOC_ROCKCHIP_HDMI
enable ROCKCHIP_HDMI ASoC driver to report jack status.

Signed-off-by: XiaoTan Luo <lxt@rock-chips.com>
Change-Id: I180161b64878c34bda0e5b7bd354cc993d8abee9
2021-11-23 10:43:12 +08:00
XiaoTan Luo
e03ac60bd0 ASoC: rockchip: add machine driver for hdmi audio
this patch is used for rockchip HDMI audio output.

Signed-off-by: XiaoTan Luo <lxt@rock-chips.com>
Change-Id: I577179e7563ad241014d023da12af1e622e84c9a
2021-11-23 10:43:12 +08:00
shengfei Xu
5a55442ff1 regulator: rk806: support shutdown/reset function
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I3fecda310463dd183bb85adc0671f356ff81cd1a
2021-11-23 10:28:51 +08:00
Tao Huang
439876311b video/rockchip: rga2: depends on !ROCKCHIP_MULTI_RGA
prevent select RGA2 and MULTI_RGA both.

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I822dc6bed24cae7c86135cf1b4af0cfc6e681240
2021-11-23 09:45:34 +08:00
Lin Jinhan
df3b2a9643 crypto: rockchip: core: modify buffer addr_vir size to 8 PAGES
Increase the buffer size from 1 to 8 pages. Data can be copied to
 the buffer for hardware crypto calculation when the scatter list
 does not meet the alignment requirement and data length less than
 8 pages.

Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: Id5e36f4fa7fc042ea4d117071ae9fee16ebb3494
2021-11-22 21:27:39 +08:00
Lin Jinhan
6ad785b40f crypto: rockchip: v1&v2: switch ablkcipher to skcipher API
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: I2936c26d1a9600ecbdb86ab2821a502371e9c2bc
2021-11-22 21:24:44 +08:00
Damon Ding
3a84f255cd arm64: dts: rockchip: rk3588: add support for BT656
add dts file:
	rk3588s-evb3-lp4x-v10-rk630-bt656-to-cvbs.dts

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I82e7bf46ed0c6c0a3a35c9528a026d24bf2cfc43
2021-11-22 21:19:12 +08:00
Damon Ding
48801131ab arm64: dts: rockchip: rk3588: add support for BT1120
add dts file:
	rk3588s-evb3-lp4x-v10-sii9022-bt1120-to-hdmi.dts

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I985b763ccaecc6aa94010da92bbad962b1562a45
2021-11-22 21:17:23 +08:00
Damon Ding
1ed78e4f4e arm64: dts: rockchip: rk3588: add pinctrl of bt656 mode
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Ia659d2b486aa31fd36fc04c971620894e9db1d7e
2021-11-22 21:16:22 +08:00