The analogix_dp_read()/analogix_dp_write() help workaround async
issue between pclk clock and 24m clock. See the following commit
for details:
commit 33f5d1439f ("drm/bridge: analogix_dp: Workaround async issue between pclk clock and 24m clock")
Change-Id: I41a0767184bfbfc5bcacceb2177189836dcc9e90
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
During the reset process, some threads may still be accessing the
flash, which will affect the soft reset behavior of the subsequent
startup process. For example, the MXIC device may not meet the tREADY2
timing, so it is necessary to avoid flash access during the reset
process.
Change-Id: Ibb0aa2791a83ec820d7352c9558d3a962a2bf66d
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
SPI Nor usually has a way to obtain the CR status and add a warning
to notify developers to make corresponding optimizations to avoid
forced SR writing, which may cause SR wear out.
Change-Id: Id0e32b94c33f564539cbbac3bb2147ad8227c3dd
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
All winbond particles support 35H command, but some particles do
not accurately feedback information after SDFP param parsing.
Change-Id: I00ad45ccd7ca7f7798a2c0699d064a58c6e411c6
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Configure pcie30phy phy_grf with clk PCLK_PHP_ROOT on.
Change-Id: Ie3f9fa78aaf7b1098450ade48e6f0c9f09725869
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
enable too early may lead to mipi csi2 overflow
Change-Id: Ib4d1f59803b8dcfdea8ba219fe8dc9667db35428
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Avoid commit new plane time close to vsync at async mode, the following
case maybe lead to error:
vsync[1]->update plane[2]->config done[3]->update plane[4]->vsync[5]
If new vsync[5] insert step 4, only part of plane register complete,
this will lead to part of plane register take effect and lead to error.
So we introduce this safeguard, when commit time exceeds 15/16 of a
frame, this frame will be postponed to the next frame.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I4e405baf6ac080f6990e94f639c168ff9f0daf1c
The vop2_win_disable() may be called multiple times in a short period
before the fs comes. Using VOP_WIN_GET(vop2, win, enable) for
judgment may cause double disable of win, leading to double decrement
of vop2_power_domain.ref_count.
This patch uses regbak to determine whether win is already disabled
in vop2_win_disable(), similar to what is done in the
vop2_win_enable().
Change-Id: I3095ef0ef0068ef3dd7245375127083a17871341
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
If the power domain has a parent power domain, the ref_count of
parent power domain should also be set during initialization.
Change-Id: I4948d11fee2829049559541040ae2117ca319329
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
If the PD has already been turned off, and the value of
vop2_power_domain.ref_count is zero at this time, calling
vop2_power_domain_put() again will cause ref_count to underflow.
This underflow will be interpreted as if the PD has been turned on.
Fixes: aa3aee14d0 ("drm/rockchip: vop2: Add vop2 internal pd support for rk3588")
Change-Id: Ia814c5907072cd1aee785734e36053cba7382b23
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
When do 'echo 1 > /proc/sys/abi/swp' on two cpus at the same time, we can see:
call_undef_hook() at traps.c:442
do_undefinstr() at traps.c:504
el0_undef() at entry-common.c:605
el0t_64_sync_handler() at entry-common.c:689
el0t_64_sync() at entry.S:585
That is because write swp 1 at the same time, add the swp_hooks to the undef_hook
list twice, swp_hooks list node's next becomes itself. When list_for_each_entry of
the undef_hook, cpu loops forever here.
Change-Id: Ice60dbc633020220e7218a554e9d0e4c7dacceb4
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Previously, Valhall and Bifrost GPUs shared a single driver source directory (drivers/gpu/arm/bifrost).
However, starting from DDK r52 (g27), Bifrost GPUs are no longer supported.
As a result, the Valhall GPU driver from DDK r53 (g28) must use a separate source directory
(drivers/gpu/arm/valhall).
There are also modifications in some header files outside of drivers/gpu/arm/.
In addition, the configs related to Bifrost and Valhall GPUs have been removed
from the defconfig file like rockchip_linux_defconfig,
which does not reflect the current SoC.
Instead, these configs have been migrated to the .config files
such as rk3576.config, whose file names can reflect the current SoC.
Therefore, for some SoCs, the kernel compilation command line needs to be adjusted.
Change-Id: I0c4384212b4b679a728401f7f89ae839530f002b
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
