1. The cluster DRM_FORMAT_YUYV refers to fbc YUV422 format, and need
config win data format as h06: YCbCr422;
2. The esamrt DRM_FORMAT_YUYV refers to LINEAR YUYV422 format, and
need config win data format as h08: YVYU422;
3. RK3576 and earlier platforms, for FBC data, only the format
configured in the AFBC register is used. Even if the win format is
incorrectly configured, it does not affect current operations, but
future platforms will rely on this win format, so it must be
configured correctly.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I5b116f226dd2d8f905c79338c03c659156683e20
some plane can't support scale up/down the win->regs->scl is undefined.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ia103dcd0f2a805cba1ec0acfffe049e617fc5520
Adding the register definition for port_extra_en can improve compatibility.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I0d9dd3ab31662c97e7c7fb870597b192fb2cda75
Adding the register definition for dsp_vcnt can improve compatibility.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ibd9a181834031fe2fd2d83eb1735b70ec1de3187
The win_data structure provides a more accurate way to obtain each
plane’s maximum input and output size.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I11cc40b9886235079d2e03d3a4ef64649bd32659
Splitting win_alpha_map into alpha_map_en and alpha_map_val ensures
better compatibility with next SOC.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Idcc62e2201c212bbd4fcb37c6256823301b70af6
It is more reasonable to store win_alpha_map in the vop2_win_regs.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I70979911a3454608f51036322c57bb5b35fe81cb
To deal with bottom_layer_global_alpha when only have one esmart layer
at bottom layer. And the cluster global alpha is processed by cluster mix.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I1f5de9774920a37a60d45c77c1f71bc740bbbb7a
add support layer0 do global or pixel alpha with background layer,
include premulti or nonpremulti pixel alpha.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I67fb6764999098064506de63cddf58e34ab1765f
In AOR mode, the DMA count does not need to correspond
to the AAD frame count, and the maximum DMA count range
can be used, such as 16-bit 0 to 65535 in RV1126B.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Change-Id: Ia5143d788d2c7fb142ffd453e25fbf2aa867348b
Originally, there was no DRM framework to invoke the serdes enablement
process
Change-Id: I5ab31c2f712cf410c1537f5ef2dffbaa015d14ee
Signed-off-by: Zitong Cai <zitong.cai@rock-chips.com>
To slove the error:
the communication(spi-write) has a half-level problem.
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I93af4cb501d9076f5d5d9a0a3605406e2dc4b1c4
- Deleted the &rockchip_suspend node and all suspend-related GPIO/IO
configurations to clean up the device tree.
- Simplified and consolidated the include statements to only reference
rv1126b-evb2-v10.dts.
Change-Id: Ic0e0afdb58ae6868896fca6544939396d04cd9f7
Signed-off-by: Leo Sun <leo.sun@rock-chips.com>
Disable overdrive opps by default, and enable them in board dts if
use overdrive mode.
Change-Id: I6db9bd54b727aa3723a2cf46e1b5bd40bdeca0d9
Signed-off-by: Liang Chen <cl@rock-chips.com>
When using the ZME algorithm for scaling, the scaling config needs to
be adjusted to ensure performance:
If plane height >= half of display height:
- Use gt4 when down-scaling ratio > 8×
- Use gt2 when down-scaling ratio > 4×
Otherwise:
- Use gt4 when down-scaling ratio > 6×
- Use gt2 when down-scaling ratio > 3×
Change-Id: I50ce653134dc697d64134ce7aa8f98a2d0e8262b
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
When sample rate changes, a reset operation is performed, and another
reset occurs after debouncing. This results in less data being read
by upper layer, thus triggering an underrun condition.
Therefore, remove reset operation in rk_spdifrx_trigger. Meanwhile,
when sample rate changes, disable dma enable, and after debouncing
completes, notify upper layer via stop_xrun to restart, then enable
dma to resume data transfer.
Change-Id: Ie112ed83018722d069bd85d181f609c4bf865027
Signed-off-by: Zhong Shengquan <shengquan.zhong@rock-chips.com>
Add a debounce timer to prevent continuous reporting of SYNC/NSYNC
information during plug-in and unplug operations.
Add the capability to detect non-linear pcm data and sample bit width,
then notify the application layer of the results.
Add a fifo timer to detect real-time data inflow in the rx fifo,
supporting glitch-free sampling rate transitions.
Add a configuration option for the always-on clock feature.
Change-Id: Ifb7bd55e9eefb6e07d00e16de12abff43d7e4d4e
Signed-off-by: Zhong Shengquan <shengquan.zhong@rock-chips.com>
Obtain the transmitter's sample rate through channel status bits,
and use the CDRST register and MCLK to estimate the sample rate.
Notify sync and sample rate information through controls.The control
names are "RK SPDIFRX SYNC STATUS" and "RK SPDIFRX SAMPLE RATE". The
application layer needs to monitor the controls and read the control
values to obtain the information.
For the sync control, 0 indicates an unlocked state, and 1 indicates
a locked state. The sample rate control has two values, the first
represents the sample rate obtained from the channel status, and the
second represents the estimated sample rate.
Change-Id: Ie3b4f009c55d326c4517996efa46e6e2e31c7d65
Signed-off-by: Zhong Shengquan <shengquan.zhong@rock-chips.com>
