set pll sequence:
->set pll to slow mode or other plls
->set pll down
->set pll params
->set pll up
->wait pll lock status
->set pll to normal mode
To slove the system error:
rockchip_rk3399_wait_pll_lock: timeout waiting for pll to lock
rockchip_rk3399_pll_set_params: pll update unsucessful,
trying to restore old params
Change-Id: I62aecd9f292de5a3c7bcd8a87231785bf115159d
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
If setting freq is not support in rockchip_pll_rate_table rk3399_pll_rates[],
It can set pll params by auto.
Change-Id: I5016cece64dca4c2efec18d552ee6be426f6b95a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The rk3399 hdmi phy is supplied by the vpll directly and needs to adapt
that frequency depending on the selected resolution on the hdmi output.
For the hdmi-phy the vpll frequency is supplied unchanged without
any dividers being present there.
The vpll also is one of the sources the general display clock of the
visual output processor (vop) and as it is somewhat special for
display operations possibly also the preferred pll source. Here a divider
is available between the pll-mux and the vop clock, so that this part
can adapt the resulting frequency if needed.
So to keep the vop clock in line with the target rate, set the newly
introduced CLK_KEEP_REQ_RATE flag for the dclk_vop clocks on rk3399.
(am from https://patchwork.kernel.org/patch/8993771/)
Change-Id: Iba9a179b764472f22d7531eb0c662dcd982433d4
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Given a hirarchy of clk1 -> [div] -> clk2, when the rate of clk1 gets
changed, clk2 changes as well as the divider stays the same. There may
be cases where a user of clk2 needs it at a specific rate, so clk2
needs to be readjusted for the changed rate of clk1.
So if a rate was requested for the clock, and its rate changed during
the underlying rate-change, with this change the clock framework now
tries to readjust the rate back to/near the requested one.
The whole process is protected by a new clock-flag to not force this
behaviour change onto every clock defined in the ccf.
(am from https://patchwork.kernel.org/patch/8993761/)
Change-Id: Ie2636710cb4e66815ee45b28ec86eeaaa47c55c7
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add usic node for rk3399 USB 2.0 EHCI controller
with usic phy.
Change-Id: Ibb4179ff1479816daa3b8455b0229f8a7a05bbdf
Signed-off-by: William Wu <william.wu@rock-chips.com>
mcu run at 97MHz to reduce lpddr4 scale frequency elapsed time
Change-Id: Ie2805eaf0d902c9531819217d05a86775d85f809
Signed-off-by: CanYang He <hcy@rock-chips.com>
Rk3399 vopb's gamma table size is 1024, vopl's gamma
table size is 256
Change-Id: Iea9cd70f82dfa9c9c8ae53a24c8153eebb981e7a
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Right now only one driver support vpu and rkvdec,
so move the nodes from rk3399-android[-next].dtsi to rk3399.dtsi.
Change-Id: Id908843774ed8eede3aeddb24059ae92a35e5b98
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
The opp who contains a opp-suspend property will be configured
during suspend or reboot.
Change-Id: I6b2eede43216435f568db6959127a6e84c8cd4c8
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Make sure the aclk_gpu freq is safety.
After soft reset the vdd_gpu is maintain
the voltage value before reset.
Change-Id: I3509b211d74cf649067090d13ce20d5c62782fd7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
To support ddr frequency scaling function, we need
enable dmc and dfi node.
Change-Id: I84ea6bff679365d86937ff10bcdf466ea31901fb
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
1. modify clock-names, according to Heiko's suggestion, clock names
should always be in the scope of the device block (named after what
it supplies), and clock-names are always meant from the perspective
of the individual ip-block.
2. remove unnecessary clocks, refer to rk3399 TRM, aclk_usb3 is the
parent of aclk_usb3otg0/1 and aclk_usb3_grf, and we will enable
aclk_usb3otg0/1 and aclk_usb3_grf, so don't need to enable aclk_usb3
again. In addition, the aclk_usb3_rksoc_axi_perf clk is used for usb3
performance monitor module which we don't use now, so don't need to
enable it.
Change-Id: I1d50a72d1523b8b70f1e5f388dc357807131dd7c
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
The DesignWare USB3 integrated in rockchip SoCs is a configurable
IP Core which can be instantiated as Dual-Role Device (DRD), Host
Only (XHCI) and Peripheral Only configurations. For rk3399, it has
two DWC3 controllers, we set DRD for DWC3_0 and Host only for DWC3_1
by default.
Change-Id: Ia0063e04e48770d8d0ec7ec86cb621c5e9979fb9
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
On upstream uboot, we use ums mode to update firmware.
Add this flag to help enter USB Mass Storage mode.
Change-Id: I0e515bfd8703bd48d950b72787b365226af11ce9
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Big cores' power consumption and gpu's are greatly reduced, ipa parameters
are ajusted accordingly.
Change-Id: Ibfdae1856c2f1c2cf80a0a2f963ec878053c6ef0
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Big cores' power consumption is as much as 8 times of little cores'.
Eas tends to bring tasks to big cores to assure the performance, and
this will make the temperature of soc out of control. To resolve this
issue, we set the power request weight of both little cores and gpu is
10 times of big cores, when temperature control occurs. Meanwhile, we
decrease passive polling interval to make temperature control more
accurate.
Change-Id: Ib01948c6a4f4383f03f1317b2397f07fbdc3487e
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
according to our testing results, added the ipa parameters for both cpu
big cores and cpu little cores, and updated the parameters for gpu.
for now,the gpu thermal zone is used only to get the gpu's temperature.
Change-Id: Ifc7708de9d880e0f9cd5da0bb71a135b0c381b45
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
We don't need to reference the pmugrf/grf in the clock driver any more.
Change-Id: Ibda203163c84ab4004e1225e5868267024069199
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
It will cause deadlock and while(1) if call printk while schedule
is in progress. The block state like as below:
cpu0(hold the console sem):
printk->console_unlock->up_sem->spin_lock(&sem->lock)->wake_up_process(cpu1)
->try_to_wake_up(cpu1)->while(p->on_cpu).
cpu1(request console sem):
console_lock->down_sem->schedule->idle_banlance->update_cpu_capacity->
printk->console_trylock->spin_lock(&sem->lock).
p->on_cpu will be 1 forever, because the task is still running on cpu1,
so cpu0 is blocked in while(p->on_cpu), but cpu1 could not get
spin_lock(&sem->lock), it is blocked too, it means the task will running
on cpu1 forever.
Change-Id: I60d02d8c957273872f97939632bdd235accdad4e
Signed-off-by: Chen Liang <cl@rock-chips.com>
Indeed, the values of the model parameters are supplied by Rocky Hao.
Change-Id: I23edaa0ee104d07f79f5bf5bdbd393b4fb3c5120
Signed-off-by: chenzhen <chenzhen@rock-chips.com>
400MHz and 600MHz aren't supported at present.
This had submitted in commit a8c497e79d
("arm64: dts: rockchip: rk3328: Disable 400MHz and 600MHz for dmc")
but was modified in commit 59af91b563
("arm64: dts: rockchip: auto select opp-table by leakage for rk3328")
by mistake.
Change-Id: I864453d16596798e063a2c3569b260fd1a95c209
Signed-off-by: Liang Chen <cl@rock-chips.com>
If show logo in uboot, can't change vop clocks.
Change-Id: Ia149b452e16dedcafaa15bfa5d5dc989b06737ff
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
