ov50c40's register settings all set mirror bit 1,
but current bayer pattern is corresponding to no mirror,
so fix it.
Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: I9145955a20e82b1985ed7e84f8f51de3697b0b96
When increase voltage the cpu frequency is increased at the same time,
but the read margin has not been reduced.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I97097a5114abad193b7a29aeada390d0323b10ba
Dp and hdmi need setting precise clock, if the clock source can't
generator the precise clock for a display mode, the display mode
will be filter in mode valid previous.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I9ec86296a8332368d9f851640c7e8d067a0d96c3
when get edid failed or the edid not set the bpc and color format,
we need set a default value.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Signed-off-by: Wyon bi <bivvy.bi@rock-chips.com>
Change-Id: Icf8a7104c8d16e38f276dc74ac4df20108adf6fb
In hdmirx audio the cpu dai may act as slave
And there also will be multi dai cells to select
Signed-off-by: Shunhua Lan <lsh@rock-chips.com>
Change-Id: I9b68a064204bb443b7e1e6fdc6e7f9e23b70e902
We notice a pd0 off timeout at system resume.
This because we set pd_off_imd before vop suspend.
but this will case VOP POWER_CTRL regisert record some
wrong state, and will lead a POWER_CTRL register value
change unexpectedly.
So we reset axi clk to clear this state at vop2_inital
to avoid the wrong register state.
[35.874922] [drm:vop2_crtc_atomic_enable] Update mode to 1080x1920p60, type: 16 for vp3 dclk: 132000000
[35.875412] [drm:vop2_crtc_atomic_enable] dclk_out3 div: 0 dclk_core3 div: 0
[35.875424] [drm:vop2_crtc_atomic_enable] set dclk_vop3 to 33000000, get 33000000
[35.885838] <<GTP-INF>>[gt1x_request_event_handler:1093] Request Reset.
[35.885866] <<GTP-INF>>[gt1x_reset_guitar:784] GTP RESET!
[36.073639] [drm:dw_mipi_dsi2_encoder_enable] final DSI-Link bandwidth: 880 x 4 Mbps
[36.141834] [drm:vop2_wait_power_domain_off] *ERROR* wait pd0 off timeout
Fixes: 8684b9914503("drm/rockchip: vop2: power off all vop pd when enter
suspend mode")
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I974573163e35e10dc0748aadc4966219465ed603
the rk806 sleep mode may cause the system to shut down unexpectedly.
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I5e2b7ebe277d7e8ec417feac88be5c167657d833
RK3588 dclk is required to access hdmi grf register.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ia7a2f2ab18d8734696b9493340f206aad0168d4c
When the display interface is BT656. the register of
core_dclk_div_sel should always be set 1. Not only 'i'
modes like 480i and 576i, but also 'p' modes like 720p,
both need this setting.
As for BT1120 and other interfaces, this bit should be
1 when display mode belongs to 'i', and 0 when display
mode belongs to 'p'.
Only RK3568 has the core_dclk_div_sel control bit, which
has been removed on RK3588.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: If67614bc5068024d602c6acbbe9676d6245fdf1a
the uboot rk8xx_pwrkey driver requires the pwrkey node to be configured
to okay status.
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I7892fd5c845cfe870d731b3d92b5a501baac732a
1. it is not need save qos when resetting.
2. In the ccu mode, force core idle is an asynchronous operation.
while the core may still be working and will report irq.
However, since it is currently a reset operation, IRQ can directly
disabled without processing.
Change-Id: I2b32f1fdaf77ecf244ae15fdf22341f55b7f3ffc
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
Keep dclk:v_pixclk = 1:1 for HDMI RGB/YUV444.
Keep dclk:v_pixclk = 1:2 for HDMI YUV420.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I54bf735be6c1ad2bfa976cbbeb685d5a49a8beeb
This is an ineffective change, and accessing the register after
HDMI disabled will cause system crash.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I0633f83fcdf4abaff1e8f72fe3c9f7845c492a2e
Decrease RK_CRYPTO_PRIORITY from 300 to 0.Hardware driver
will only invoked by user layer through the driver name.
Change-Id: Ifeda13a2b9ce6fec6be60a2422b7507f91eedbb5
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
