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550 Commits

Author SHA1 Message Date
zhangqing
7c8d2e7bae rk312x:clk:select gpll_div2 when set apll,set aclk_core div 2014-09-19 14:41:13 +08:00
陈亮
eb7e8235cf rk312x: correct clk_ddr rate 
Signed-off-by: 陈亮 <cl@rock-chips.com>
 2014-09-18 02:33:31 -07:00
张晴
0a1c7b39a3 rk312x:clk:fixed frequency div for aclk_core and pclk_dbg 2014-09-04 14:47:06 +08:00
黄涛
c7412991e9 Merge remote-tracking branch 'origin/develop-3.10' into develop-3.10-next 
Conflicts:
	arch/arm/mach-rockchip/vcodec_service.c
	drivers/input/Makefile
 2014-08-08 10:21:50 +08:00
黄涛
fcef60e36f Merge tag 'lsk-v3.10-android-14.07' into develop-3.10 
LSK v3.10 Android 14.07 release

Conflicts:
	drivers/clocksource/arm_arch_timer.c
	lib/Makefile
 2014-08-06 15:34:14 +08:00
张晴
97a6355e4a rk312x:clk:support clk pd,set cpll for any freq 2014-08-01 10:48:01 +08:00
陈亮
6ad8034c50 Revert "rk312x: set clk_ignore_unused = true" 
This reverts commit f0db0fef3b.
 2014-07-31 06:07:55 -07:00
陈亮
f0db0fef3b rk312x: set clk_ignore_unused = true 
Signed-off-by: 陈亮 <cl@rock-chips.com>
 2014-07-31 06:06:33 -07:00
张晴
349186ee54 rk312x:clk:support set pll clk and modify init clocks 2014-07-22 17:46:27 +08:00
Alex Shi
d0bc082b9c Merge tag 'v3.10.49' into linux-linaro-lsk 
This is the 3.10.49 stable release
 2014-07-18 14:08:02 +08:00
张晴
a013c410ce rk312x:clk:support set clks 2014-07-18 10:04:19 +08:00
张晴
e30ce9d6d4 rk3036:clk:modify clk_pll.c error 2014-07-18 09:50:07 +08:00
张晴
c5e90190f9 rk3036:clk:add others freq,modify apll 1000M by init 2014-07-18 09:44:30 +08:00
Thomas Gleixner
57b30c333f clk: spear3xx: Use proper control register offset 
commit 15ebb05248 upstream.

The control register is at offset 0x10, not 0x0. This is wreckaged
since commit 5df33a62c (SPEAr: Switch to common clock framework).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2014-07-17 15:58:02 -07:00
张晴
bf9fcb917c rk3036:clk:modify init clocks,modify pclk_dbg freq div 2014-07-17 17:38:39 +08:00
黄涛
c1d0a2d670 Revert "rockchip:mali400:tmp not disable mali clk ,enable mali runtime pm" 
This reverts commit 8c503dc354.
 2014-07-15 17:05:33 +08:00
xxm
8c503dc354 rockchip:mali400:tmp not disable mali clk ,enable mali runtime pm 2014-07-15 15:02:15 +08:00
张晴
032de7a4eb rk3036:clk:rename clk_core_pre to clk_core 2014-07-09 16:50:25 +08:00
张晴
b365f68f64 rk3036:clk:modify init clocks 2014-07-09 08:55:04 +08:00
黄涛
223378cc0f Merge remote-tracking branch 'origin/develop-3.10' into develop-3.10-next 
Conflicts:
	drivers/mmc/host/Kconfig
	drivers/video/rockchip/hdmi/chips/rk616/rk616_hdmi.c
	drivers/video/rockchip/hdmi/chips/rk616/rk616_hdmi.h
	drivers/video/rockchip/hdmi/chips/rk616/rk616_hdmi_hw.c
	drivers/video/rockchip/hdmi/chips/rk616/rk616_hdmi_hw.h
	include/linux/mmc/rk_mmc.h
	include/linux/rockchip/cru.h
 2014-07-07 21:01:04 +08:00
张晴
c46a7d3bfd rk3036:clk:support set pll clks and init clocks 2014-07-07 14:06:37 +08:00
xxx
f4f515221a add arm pll rate conf 2014-06-26 18:17:08 +08:00
dkl
22bab315d1 clk: rk3288: modify RK3288_LIMIT_PLL_VIO0/1 
This commit corresponds to commit debf1d2237.
 2014-06-24 18:00:38 +08:00
dkl
e288a66e3d clk: rockchip: pll: use reg offset instead of reg 2014-06-18 09:27:53 +08:00
dkl
c8045b4caa clk: rockchip: add support for uboot display 2014-06-16 19:47:27 +08:00
dkl
79ef987e89 iclk: rk3288: set hclk_vio when clk_3288_dclk_lcdc0_set_rate 2014-06-12 18:09:19 +08:00
Alex Shi
3b8d7f4db3 Merge tag v3.10.42 into linux-linaro-lsk 
This is the 3.10.42 stable release
 2014-06-09 12:55:42 +08:00
Dan Carpenter
c4f3c998c1 clk: vexpress: NULL dereference on error path 
commit 6b4ed8b00e upstream.

If the allocation fails then we dereference the NULL in the error path.
Just return directly.

Fixes: ed27ff1db8 ('clk: Versatile Express clock generators ("osc") driver')
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2014-06-07 13:25:35 -07:00
dkl
0a450169ab clk: rk3288: when apll change rate, adjust div to make rate change more gently 2014-05-28 17:45:06 +08:00
dkl
9f004277ef clk: rockchip: add rk3188plus_pll_com_table and some marcos, to 
separate CLK_PLL_3188PLUS pll type from CLK_PLL_3188 better.
 2014-05-28 15:14:19 +08:00
dkl
b4cae74732 clk: pd: rockchip: add notify when clk_pd_prepare/unprepare 2014-05-14 14:00:47 +08:00
dkl
64fddf4e59 clk: rk3288: keep arm_gpll enable when rk3288 apll set_rate 2014-05-13 14:34:07 +08:00
dkl
654827f3f3 clk: rk3288: set BW 20 when GPLL is 297m for HDMI 2014-05-13 10:24:07 +08:00
Mark Brown
07e633984a Merge remote-tracking branch 'lsk/v3.10/topic/of' into linux-linaro-lsk 2014-05-12 19:10:50 +01:00
Mike Turquette
5e657ef3fc clk: of: helper for determining number of parent clocks 
Walks the "clocks" array of parent clock phandles and returns the
number.

Signed-off-by: Mike Turquette <mturquette@linaro.org>
(cherry picked from commit f61027426a)

Signed-off-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
 2014-05-12 19:06:11 +01:00
dkl
6cff575b83 clk: pd: rockchip: add notify when clk_pd_enable/disable 2014-05-09 14:50:21 +08:00
dkl
d86c0abe7f rk3288: fix the bug when dclk_lcdc select gpll as parent 2014-04-30 18:17:16 +08:00
dkl
d64a67250b rk3288: set RK3288_LIMIT_PLL_VIO1 to 410MHZ 2014-04-30 09:25:32 +08:00
dkl
ad11a1286b clk: rockchip: add CLK_SET_RATE_PARENT_IN_ORDER 
If the flag CLK_SET_RATE_PARENT_IN_ORDER is set, consider the
order of .set_parent and .set_rate, to prevent a too large
temporary rate on rate change. This will fix the bug of clk_gpu
in rk3288.
 2014-04-28 21:24:24 +08:00
dkl
7348c1bed5 clk: rockchip: rk3288: adjust clock settings 
1. add clkops_rate_3288_dclk_lcdc0/1
2. change gpll init_rate to 297M, and npll init_rate to 1250M
 2014-04-28 21:24:24 +08:00
dkl
91019ca759 clk: rockchip: add clk_pll_ops_3188plus_auto 2014-04-28 21:24:24 +08:00
黄涛
193836a164 clk: rockchip: support dump cru register when panic 2014-04-23 17:56:36 +08:00
dkl
5a6a7c9fe3 clk: rockchip: add clkops_rate_3288_usb480m 2014-04-17 11:18:10 +08:00
dkl
d1de807ce5 pd: rockchip: add virtual pd clks 2014-04-14 21:32:41 +08:00
dkl
54775cd3b8 pd: rockchip: add clk_pd type and rk3288 clk_pd support 2014-04-14 16:59:23 +08:00
陈亮
2a9f4cb9de rk3288-tb: adjust clk core dvfs table; init vdd_logic by ddr dvfs table 2014-04-01 03:15:18 -07:00
dkl
2b4b8a080a clk: rockchip: rk3288: fix APLL 48M\126M setting 2014-04-01 11:53:09 +08:00
dkl
c0acf5da01 clk: rockchip: add rkclk_init_enable and open rk3288 gating 2014-03-31 14:04:16 +08:00
dkl
fcbd12ce01 clk: rk: add RKCLK_FIXED_RATE_TYPE and RKCLK_FIXED_FACTOR_TYPE 2014-03-27 15:21:13 +08:00
dkl
0e321ec4d7 rk3288: fix problem of mux clk with frac parent in rk3288 
Mux clk with frac parent in rk3288, like i2s/spdif/uart,
has problem when set rate before.
 2014-03-25 20:16:37 +08:00